A chip package assembly includes a first high-power chip, a second low-power chip, a thermal cooling device and a heterogeneous thermal interface material (HTIM). The thermal cooling device may overlie the first chip and the second chip. The HTIM includes a first thermal interface material (TIM) and a second TIM. The first TIM overlies the first chip, and the second TIM overlies the second chip. The first TIM includes a material that has a first thermal conductivity and a first modulus of elasticity. The first TIM can reflow when the first die reaches a first TIM reflow temperature. The second TIM comprises at least a polymer material. The second TIM has a second modulus of elasticity that is greater than the first modulus of elasticity and a second thermal conductivity that is less than the first thermal conductivity.

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

A semiconductor device includes: a baseplate; an insulating substrate on the baseplate; a semiconductor element on the insulating substrate; a case bonded to the baseplate by an adhesive, the case surrounding a space in which the semiconductor element is positioned; and an encapsulating material filling the space surrounded by the case, in which, the case includes a claw, the claw includes: a protrusion protruding from an inner wall surface of the case; and a hook inclined from the protrusion, a space being sandwiched between the hook and the inner wall surface of the case.

Various embodiments of the teachings herein include a sintered power electronic module with a first plane and a second plane different from the first plane. An example comprises: a first substrate with a first metallization arranged on the first plane; a second substrate with a second metallization arranged on the second plane; a switchable die having a first power terminal and a second power terminal, the die arranged between the first substrate and the second substrate; and a surface area of all the sintered connections of the first plane is between 90 and 110% of a surface area of all the sintered connections of the second plane. The first power terminal of the die is joined to the first metallization via a sintered connection in the first plane and the second power terminal is joined to the second metallization via a sintered connection in the second plane.

A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.

In an embodiment of the present inventive concept, a high bandwidth memory includes a base die, and a semiconductor stack disposed on the base die, the semiconductor stack comprising a plurality of underfill members and a plurality of memory dies that are alternately stacked. Each of the plurality of underfill members includes first sides, each of the plurality of memory dies includes second sides, and each of the first sides is recessed from a corresponding second side.

A semiconductor package includes: a package substrate, a first chip on the package substrate, a second chip on the package substrate and spaced apart from the first chip in a horizontal direction, a third chip having a film adhesive layer attached to a lower surface thereof, and attached to the first chip and the second chip, a first fillet adhesive layer surrounding a side surface of the first chip and in contact with a portion of the lower surface of the third chip, and a second fillet adhesive layer between the second chip and the third chip. A vertical level of an upper surface of the first chip is higher than a vertical level of an upper surface of the second chip, and the second fillet adhesive layer protrudes from the upper surface of the second chip in the horizontal direction.

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure, a first interposer, a second interposer, a first semiconductor die, and a second semiconductor die. The substrate structure has a first surface and a second surface opposite to the first surface. The first interposer is disposed over the first surface of the substrate structure. The second interposer is disposed over the first interposer. The first and the second semiconductor dies are disposed over the first surface of the substrate structure, and the first and the second semiconductor dies are bonded to two opposite sides of the second interposer, respectively. The substrate structure includes a thermal enhancement portion, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from that of other portions of the substrate structure.

A method of manufacturing a semiconductor package includes mounting a first semiconductor die over a package substrate, forming a first connector to electrically connect the first semiconductor die to the package substrate, offset-stacking a second semiconductor die over the first semiconductor die in a first direction, offset-stacking a third semiconductor die on the second semiconductor die in a second direction, offset-stacking a fourth semiconductor die on the third semiconductor die in the second direction, forming a second connector to electrically connect the second semiconductor die to the package substrate, forming a third connector to electrically connect the third semiconductor die to the package substrate, and forming a fourth connector to electrically connect the fourth semiconductor die to the package substrate.

A semiconductor package includes first semiconductor chips stacked on a package substrate, a lowermost first semiconductor chip of the first semiconductor chips including a recessed region, and a second semiconductor chip inserted in the recessed region, the second semiconductor chip being connected to the package substrate.