An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.

One aspect of the present disclosure pertains to a package structure. The package structure includes a die bonded to a substrate, where a plurality of first channels are formed on a top surface of the die; a lid bonded to the substrate and over the die; and a thermal interface material (TIM) disposed between and contacting the lid and the die, where the thermal interface material fills the first channels.

A package structure includes a package substrate, a semiconductor module on the package substrate, a composite thermal interface material (TIM) layer including liquid metal in a polymer matrix on the semiconductor module, a package lid on the composite TIM layer and attached to the package substrate, and a reactive interface layer in contact with the composite TIM layer on at least one of the semiconductor module or the package lid.

Provided are an electronic package and an electronic structure. The electronic package includes a carrier, an electronic component disposed on the carrier, a heat dissipation member connected to the electronic component through a thermal interface material, a backside metal layer disposed on the electronic component and connected to the thermal interface material, and a nanowire array metal layer disposed between the thermal interface material and the backside metal layer. Therefore, a displacement of the thermal interface material relative to the backside metal layer is limited by a rough surface of the nanowire array metal layer. As such, a migration of the thermal interface material and a resulting poor bonding between the heat dissipation member and the electronic component, which affect a heat dissipation efficiency of the electronic package, can be prevented.

A semiconductor package includes a substrate including a wiring; a chip stack including a plurality of semiconductor chips stacked on the substrate, wherein each of the plurality of semiconductor chips has upper and lower surfaces, opposite to each other, front and rear surfaces, opposite to each other, left and right surfaces, opposite to each other, and connection pads disposed on the upper surface adjacent to the front surface; bonding wires electrically connecting the connection pads to the wiring of the substrate; a plurality of attachment films disposed on the lower surface of each of the plurality of semiconductor chips; a mold layer covering the chip stack and the bonding wires; and connection bumps disposed below the substrate, and electrically connected to the wiring, wherein at least one of the plurality of attachment films covers the rear surface of at least one semiconductor chip among the plurality of semiconductor chips.

Electronic structures and methods of assembly are described in which a lid with pocket sidewalls is mounted on a routing substrate such that the pocket sidewalls laterally surround an electronic component and provide a barrier to outflow of the thermal interface layer outside of the pocket sidewalls, and in particular a thermal interface layer including a liquid metal film.

In examples, a semiconductor package includes a semiconductor die having a device side in which circuitry is formed; multiple copper posts coupled to the device side of the semiconductor die; a substrate coupled to the multiple copper posts by solder joints, the substrate comprising: cylindrical copper pillars extending from the solder joints on a top surface of the substrate to a bottom surface of the substrate, the copper pillars having circular or ovoid bottom surfaces exposed to the bottom surface of the substrate; and a build-up film between and physically contacting the copper pillars. The package also includes a mold compound physically contacting the semiconductor die, the multiple copper posts, and the top surface of the substrate.

A device includes: a first substrate; a second substrate; interconnects bonding the first substrate to the second substrate; and a polymer brush-based underfill layer in a gap between the first substrate and the second substrate. A method includes: attaching initiator molecules to one or more surfaces in a gap between a first substrate and a second substrate of a bonded structure, where the first substrate and the second substrate are bonded by interconnects; growing polymer chains from the initiator molecules; and annealing the bonded structure to form an underfill layer from the polymer chains in the gap.

A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.

A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, an element selected from the group consisting of: more than 0 and 1.0% by mass or less of Si, more than 0 and 0.1% by mass or less of V, 0.001 to 0.1% by mass of Ge, 0.001 to 0.1% by mass of P, and more than 0 and 1.2% by mass or less of Cu, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.