A chip package assembly includes a first high-power chip, a second low-power chip, a thermal cooling device and a heterogeneous thermal interface material (HTIM). The thermal cooling device may overlie the first chip and the second chip. The HTIM includes a first thermal interface material (TIM) and a second TIM. The first TIM overlies the first chip, and the second TIM overlies the second chip. The first TIM includes a material that has a first thermal conductivity and a first modulus of elasticity. The first TIM can reflow when the first die reaches a first TIM reflow temperature. The second TIM comprises at least a polymer material. The second TIM has a second modulus of elasticity that is greater than the first modulus of elasticity and a second thermal conductivity that is less than the first thermal conductivity.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.