A die attach film structure includes a dicing film, an insulating adhesion layer including an upper surface and a lower surface opposite the upper surface, the lower surface of the insulating adhesion layer contacting an upper surface of the dicing film and including an insulating filler, and a conductive adhesion layer contacting an upper surface of the insulating adhesion layer and including a conductive filler.

In an embodiment of the present inventive concept, a high bandwidth memory includes a base die, and a semiconductor stack disposed on the base die, the semiconductor stack comprising a plurality of underfill members and a plurality of memory dies that are alternately stacked. Each of the plurality of underfill members includes first sides, each of the plurality of memory dies includes second sides, and each of the first sides is recessed from a corresponding second side.

A method of manufacturing a semiconductor package includes the following steps. A first integrated circuit is encapsulated by a first encapsulant. A first passivation layer is formed over the first integrated circuit and the first encapsulant. A first thermal pattern is formed in the first passivation layer. A second passivation layer is formed on the first passivation layer and the first thermal pattern, wherein the first thermal pattern is exposed by a first opening of the second passivation layer. A second integrated circuit is adhered to the second passivation layer through an adhesive layer, wherein the adhesive layer is partially disposed in the first opening of the second passivation layer.

A method for bonding semiconductor dies, resulting semiconductor devices, and associated systems and methods are disclosed. In some embodiments, the method includes depositing a first material on the first semiconductor die. The first material has a first outer surface and a first chemical composition at the first outer surface. The method also includes depositing a second material on the second semiconductor die. The second material has a second outer surface and a second chemical composition at the second outer surface that is different from the first chemical composition. The method also includes stacking the dies. The second outer surface of the second semiconductor die is in contact with the first outer surface of the first semiconductor die in the stack. The method also includes reacting the first outer surface with the second outer surface. The reaction causes the first outer surface to bond to the second outer surface.

The present disclosure describes a bonded semiconductor structure and a method of forming the bonded semiconductor structure. The bonded semiconductor structure includes first and second substrates bonded with a bonding structure. The bonding structure provides high thermal conductivity and high bonding strength between the first and second substrates. The bonding structure includes bonding layers and adhesion layers, with the bonding layers including titanium oxide and the adhesion layers including titanium nitride. The method includes forming a first adhesion layer on the first substrate and a second adhesion layer on the second substrate. The method also includes forming a first bonding layer on the first adhesion layer and a second bonding layer on the second adhesion layer. The method further includes bonding the first and second substrates by bonding the first and second bonding layers together.

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

The invention relates to a sintering paste consisting of: (A) 30 to 40 wt. % of silver flakes with an average particle size ranging from 1 to 20 m, (B) 8 to 20 wt. % of silver particles with an average particle size ranging from 20 to 100 nm, (C) 30 to 45 wt. % of silver(I) oxide particles, (D) 12 to 20 wt. % of at least one organic solvent, (E) 0 to 1 wt. % of at least one polymer binder, and (F) 0 to 0.5 wt. % of at least one additive differing from constituents (A) to (E).

In an embodiment, a package includes an interposer; a first integrated circuit device attached to the interposer, wherein the first integrated circuit device includes a die and a heat dissipation structure, the die having an active surface facing the interposer and an inactive surface opposite to the active surface, the heat dissipation structure attached to the inactive surface of the die and including a plurality of channels recessed from a first surface of the heat dissipation structure, the first surface of the heat dissipation structure facing away from the die; and an encapsulant disposed on the interposer and laterally around the die and the heat dissipation structure, wherein a top surface of the encapsulant is coplanar with the top surface of the heat dissipation structure.