A circuit structure and a method of manufacturing a circuit structure are provided. The circuit structure includes a first metal line and a second metal line. The second metal line is disposed over the first metal line. At least one air gap is disposed between the first metal line and the second metal line.

A semiconductor substrate includes a substrate and a plurality of electronic components. The substrate defines a cavity. A total number of the electronic components is N, the electronic components are divided into M groups, M and N are positive integers, and M is smaller than N. The electronic components in each group are encapsulated by a first insulation layer to form a respective component module. Each of the component modules is disposed in the cavity. A second insulation layer fills the cavity and encapsulates the component modules.

A storage device includes a substrate of a memory package and a first memory die. The substrate includes a controller and a first pin pad, the first pin pad being electrically connected to the controller and defining a data channel for data communications. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a redistribution layer electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

The disclosed subject matter relates generally to structures in semiconductor devices and integrated circuit (IC) chips. More particularly, the present disclosure relates to a metal-dielectric-metal capacitor having electrically inactive metal layers arranged in an interconnect level that is below another interconnect level containing two sets of metal lines interdigitated with each other.

A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

In some embodiments, a semiconductor device is provided. The semiconductor device includes an interconnect structure disposed over a substrate, wherein the interconnect structure includes a conductive feature disposed in a dielectric layer; a first passivation layer disposed over the interconnect structure; a second passivation layer disposed over the etch stop layer; a plurality of holes and a plurality of trenches extending from an upper surface of the second passivation layer into the second passivation layer, wherein the trenches overlap the etch stop layer in a plan view; a first capacitor structure including a first conductive layer, a first insulating layer, and a second conductive layer disposed over the second passivation layer and extending into the holes; and a second capacitor structure including a third conductive layer, a second insulating layer, and a fourth conductive layer disposed over the second passivation layer and extending into the trenches.

A semiconductor device (e.g., a System on Integrated Chip (SoIC) device) is formed by vertically integrating (e.g., bonding) semiconductor dies, where each of the semiconductor dies has a front-side interconnect structure and has a backside interconnect structure. A front-side to front-side bonding process is used to bond the integrated semiconductor dies, which reduces the lengths of the communication paths between the integrated semiconductor dies. The reduced lengths of the communication paths reduce the electrical resistance and the signal transmission delay of the communication paths, thus improving the processing speed of the semiconductor device and reducing power consumption. In addition, the bonding film stack around the bonding structure of the semiconductor dies can be formed thinner, which reduces the risk of metal cracking, thus improving device reliability and production yield.

A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

A method is provided for forming a thin film resistor (TFR) and a thin film MIM capacitor (TFMIMCAP) in an integrated circuit (IC) device. A method comprises: forming a thin film layer over an integrated circuit (IC) structure; annealing the thin film layer; and forming first and second thin film elements in the thin film layer. An integrated circuit device comprises: an integrated circuit (IC) structure; an annealed thin film layer above the IC structure; and first and second thin film elements in the thin film layer.