A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer, and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

In described examples, a device includes a first and second thin film conductive regions, a thin film dielectric region, and first, second, third, and fourth vias. A first surface of the thin film dielectric region is coupled to a first surface of the first thin film conductive region, and a second surface of the thin film dielectric region is coupled to a first surface of the second thin film conductive region. The first via is coupled to a first end of the first thin film conductive region. The second via is coupled to a second end of the first thin film conductive region. The third via is coupled to a first end of the second thin film conductive region. The fourth via is coupled to a second end of the second thin film conductive region.

Disclosed a semiconductor structure includes: a substrate, including a device layer, a buried power rail, and a through silicon via, where the through silicon via is connected to the device layer through the buried power rail; a power network layer, disposed on the substrate, where the power network layer includes at least one layer of a first power array and at least one layer of a second power array, and each of the at least one layer of the first power array is connected to the buried power rail through the through silicon via; and a capacitor structure, disposed between each of the at least one layer of the first power array and each of the at least one layer of the second power array and connected to the first power array and the second power array through a lower electrode and an upper electrode of the capacitor structure respectively.

A semiconductor structure includes an active region including a semiconductor fin base, a stack of nanostructures over the semiconductor fin base, and an epitaxial feature over the semiconductor fin base and connected to at least one of the nanostructures, the active region extending lengthwise in a first direction. The semiconductor structure further includes a gate structure wrapping around each of the nanostructures, the gate structure extending lengthwise in a second direction perpendicular to the first direction, and a backside butted contact disposed directly under and electrically connected to the epitaxial feature and the gate structure. A portion of the backside butted contact extends into the gate structure and the epitaxial feature.

A resistor structure is provided. The resistor structure includes a substrate, a first well region formed in the substrate, a poly layer over the first well region, an isolation structure disposed between the poly layer and the first well region, and an interconnect structure. The poly layer has a first end, a second end and a point between the first and second ends. The interconnect structure is electrically connected between the point of the poly layer and the first well region.

A semiconductor device includes a substrate having a front surface and a rear surface. The device includes a first transistor disposed on the front surface of the substrate and including a first gate electrode and first source/drain patterns disposed adjacent to the first gate electrode. The device includes a front surface dummy stack structure disposed on the first transistor and electrically floated, the front surface dummy stack structure extending from a lower end to an upper end, the lower end being spaced apart from the first transistor. The front surface dummy stack structure includes alternately stacked front surface dummy vias front surface dummy wires that overlap the first gate electrode such that heat generated in the first transistor is transferred to the upper end of the front surface dummy stack structure through the plurality of front surface dummy vias and the plurality of front surface dummy wires.

A method is provided for forming a thin film resistor (TFR) and a thin film MIM capacitor (TFMIMCAP) in an integrated circuit (IC) device. A method comprises: forming a thin film layer over an integrated circuit (IC) structure; annealing the thin film layer; and forming first and second thin film elements in the thin film layer. An integrated circuit device comprises: an integrated circuit (IC) structure; an annealed thin film layer above the IC structure; and first and second thin film elements in the thin film layer.

A semiconductor device includes a wiring layer, a dielectric layer covering the wiring layer, a thin film resistor provided on the dielectric layer, and a plug electrode connecting the thin film resistor to the wiring layer. The plug electrode includes a barrier layer and a buried layer. The buried layer is configured by the filling portion filling a region surrounded by a first incline surface, and an extension portion extending from the filling portion along a second incline surface. The thin film resistor is in contact with the filling portion and the extension portion of the plug electrode. A second incline angle between the second incline surface and a main surface of a semiconductor substrate is smaller than a first incline angle between the first incline surface and the main surface of the semiconductor substrate.