Systems, devices, and methods for high die stack packages with vertical die-to-die interconnects are provided herein. A die stack package can include a substrate, a lower die stack carried by the substrate, a spacer carried by the substrate, an upper die stack carried by the spacer, a plurality of wire bonds, and a plurality of vertical wires. The lower die stack can include a plurality of lower dies stacked in a cascading arrangement. The upper die stack can include a plurality of upper dies stacked in a cascading arrangement in a same direction as the plurality of lower dies. The wire bonds can electrically couple adjacent ones of the lower dies. An nth vertical wire can extend vertically between and electrically couple an nth upper die and an nth lower die. In some embodiments, the die stack package further includes an input-and-output extender carried by the substrate.

A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.

In this semiconductor device, an emitter electrode of a power semiconductor element includes a first sub-electrode provided in a region including a central portion of a front surface of a semiconductor substrate and a second sub-electrode provided in a region not including the central portion of the front surface of the semiconductor substrate. A first bonding wire connects the first sub-electrode and an emitter terminal. A second bonding wire connects the second sub-electrode and the emitter terminal. First and second voltage detectors detect voltages between the emitter terminal and the first and second sub-electrodes, respectively. It is possible to separately detect degradation of both the first bonding wire that degrades in an early period and the second bonding wire that degrades in a terminal period.

A semiconductor device includes a plurality of semiconductor elements, each of which has a first electrode, a second electrode, and a third electrode, and is subjected to an ON-OFF control between the first electrode and the second electrode in accordance with a driving signal input to the third electrode. Further, the semiconductor device includes a control terminal to which the driving signal is input, a first wiring portion to which the control terminal is connected, a second wiring portion separated from the first wiring portion, a first connection member to conduct the first wiring portion and the second wiring portion, and a second connection member to conduct the second wiring portion and the third electrode of one of the plurality of semiconductor elements. The respective first electrodes of the plurality of semiconductor elements are electrically connected to one another, and respective second electrodes of the plurality of semiconductor elements are electrically connected to one another.

A semiconductor device includes: an insulated circuit substrate including a base plate, a resin layer on the base plate, and a circuit pattern on the resin layer; a semiconductor chip that is rectangular and is bonded to the circuit pattern such that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by a predetermined distance; a case on the resin layer and surrounds the circuit pattern and the semiconductor chip; and a sealing material that covers the insulated circuit substrate and semiconductor chip and is surrounded by the case. The predetermined distance and thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip. A peripheral region of the case and a peripheral region of the resin layer are connected to each other via an adhesive layer.

A semiconductor package includes a package substrate including first and second power P-pads and first and second signal P-pads, a lower layer chip including first and second power L-pads and first and second signal L-pads, an upper layer chip offset from the lower layer chip and including first and second power U-pads and first and second signal U-pads. The first power and signal P-pads are alternatingly stacked, the first power and signal L-pads are alternatingly stacked, and the first power and signal U-pads are alternatingly stacked. The second power and signal P-pads are alternatingly stacked, the second power and signal L-pads are alternatingly stacked, and the second power and signal U-pads are alternatingly stacked. Bonding wires connect the first and second power U-pads, the first and second power L-pads, the second power U-pads and P-pads, and the second signal U-pads and P-pads.

A power module includes a first end power semiconductor element and a second end power semiconductor element. A first sum is a sum of a path length between the gate electrode of the first end power semiconductor element and a first control terminal and a path length between the source electrode of the first end power semiconductor element and a first detection terminal. A second sum is a sum of a path length between the gate electrode of the second end power semiconductor element and the first control terminal and a path length between the source electrode of the second end power semiconductor element and the first detection terminal. The power module includes a first control layer connected to the gate electrode. The first control layer includes a first detour portion that detours the path to reduce a difference between the first sum and the second sum.

A switching module includes at least one substrate, at least one switching element, at least one control loop, a first power part and a second power part. The at least one switching element is disposed on the at least one substrate. The at least one control loop is connected with the corresponding switching element. The first power part is connected with the corresponding switching element. The second power part is connected with the corresponding switching element. A direction of a first current flowing through the first power part and a direction of a second current flowing through the second power part are identical. A projection of the first power part on a reference plane and a projection of the second power part on the reference plane are located at two opposite sides of a projection of the control loop on the reference plane.

A semiconductor device according to one aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and extends in a direction forming an angle of 30 to 30 with respect to the first direction. A semiconductor device according to another aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and has a joint portion that is long in one direction in plan view and an angle of a long direction of the joint portion with respect to the first direction is 30 to 30.

A semiconductor device includes: a plurality of semiconductor elements connected in parallel; a rectifier element connected in anti-parallel to the plurality of semiconductor elements; a power terminal electrically connected to the plurality of semiconductor elements; and an electrical conductor electrically connected to the power terminal and the plurality of semiconductor elements and including a pad portion to which the plurality of semiconductor elements are bonded. The plurality of first semiconductor elements include a first element and a second element. The minimum conduction path of the first element to the power terminal is shorter than the minimum conduction path of the second element to the power terminal. The pad portion includes a first section to which the first element is bonded and a second section to which the second element is bonded. The rectifier element is located in the first section of the pad portion.