A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

A semiconductor package may include a package substrate; first semiconductor chips sequentially stacked on an upper surface of the package substrate; a second semiconductor chip on an uppermost first semiconductor chip among the first semiconductor chips, the second semiconductor chip having an overhang region protruding from one side of the uppermost first semiconductor chip and an overlapping region overlapping the uppermost first semiconductor chip, the second chip pads including first bonding pads in the overhang region and second bonding pads in the overlapping region; first conductive bumps respectively on the first bonding pads; second conductive bumps respectively on the second bonding pads; vertical wires extending from the first conductive bumps to substrate pads of the package substrate, respectively; and a molding member covering the first semiconductor chips, the second semiconductor chip, and the vertical wires.

The invention provides improved techniques for bonding devices using copper-to-copper or other types of bonds. A substrate is cleaned to remove surface oxides and contaminants and then rinsed. The rinsed substrate is provided to coating unit where a protective coating is applied to the substrate. The protective coating may be applied by immersing the substrate in a bath or via chemical vapor deposition. In an aspect, the protective coating may be copper selective so that the protective coating is only applied to copper features of the substrate. The protective coating minimizes formation of oxides and other bond weakening forces that may form during bonding processes, such as bonding a copper wire to a copper bond pad of the substrate. In an aspect, an annealing process is used to cure the protective coating and remove small imperfections and other abnormalities in the protective coating prior to the bonding process.

The present disclosure provides a memory system packaging structure and fabrication methods. The memory system packaging structure includes memory modules, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer encapsulating the memory modules and the memory controller, and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules. Each memory module includes memory dies stacked in a vertical direction. Each connecting pillar includes a first portion being in physical contact with one of the memory dies and a second portion being in physical contact with the redistribution layer.

Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.

A memory package may include a first memory die including: a first substrate; a first wiring layer on a first surface of the first substrate, the first surface being a first active surface; and a first bonding pad on the first wiring layer. The memory package may further include a second memory die including: a second substrate on the first memory die; a second wiring layer between the first surface of the first substrate and a second surface of the second substrate, the second surface being a second active surface; and a second bonding pad on the second wiring layer and electrically connected to the first bonding pad. The memory package may further include a package substrate including a first wire pad electrically connected, by a first wire, to the first bonding pad and the second bonding pad.