A power semiconductor device includes a substrate including SiC of a first conductivity type and including a first region and a second region, a drift layer of the first conductivity type on the substrate and in the first and second regions, a well region of a second conductivity type on the drift layer and in in the first region, a source region of the first conductivity type within the well region, a gate electrode on and extending along an upper surface of the well region, a source electrode connected to the source region in the first region, a metal layer connected to the drift layer in the second region, and a passivation layer covering the source electrode and the metal layer. The passivation layer defines a recessed portion between the first region and the second region.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

A semiconductor package may include a buffer die including a plurality of first wire bonding pads, a first group of core dies sequentially stacked on the buffer die, a first interposer on the first group of core dies and including a plurality of first lower connection pads in a lower surface of the first interposer to face the plurality of first wire bonding pads, respectively, a plurality of first conductive wires extending vertically from the plurality of first wire bonding pads between the buffer die and the first interposer, the plurality of first conductive wires being connected to the plurality of first lower connection pads, respectively, and a second group of core dies sequentially stacked on the first interposer.

Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.

Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.

A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.

A die including a die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, an interconnect region adjacent to the first body surface including interconnect dielectric layers with metal lines and vias, a transistor region above the interconnect region, the metal lines and vias making electrical connections to one or more power rails of the transistor region and electrically connected to transistors of the transistor region, a power region above the transistor region including an electro-conductive film on the second body surface and TSVs in the power region, an outer end of the TSV contacting the film and an embedded end of the TSVs contacting one of the power rails. A method of manufacturing an IC package and computer with the IC package are also disclosed.