An electronic device includes a carrier, a first die, and a second die. The first die is disposed on the carrier and includes a first bonding pad and a second bonding pad. The second die is disposed on the carrier and includes a third bonding pad and a fourth bonding pad. The first bonding pad is directly connected to the third bonding pad through a first bonding wire, and the second bonding pad is directly connected to the fourth bonding pad through a second bonding wire. The first bonding pad has a recessed space, and the second bonding pad is disposed in the recessed space.

An example semiconductor package includes a package substrate including a plurality of bonding pads; a plurality of semiconductor chips mounted on an upper surface of the package substrate and including a plurality of pads, respectively, where each of the plurality of pads includes first to eighth data pads; and a plurality of wires connecting the plurality of pads, respectively, where the plurality of semiconductor chips include first to fourth semiconductor chips, the first to fourth data pads included in the first semiconductor chip and the first to fourth data pads included in the second semiconductor chip are connected to each other through first to fourth wires, respectively, and the first to fourth wires are separated from the third semiconductor chip and the fourth semiconductor chip.

The semiconductor device may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. Each lower pad may be provided such that a width of a top surface thereof is smaller than a width of a bottom surface thereof. The lower pads may include first, second, and third lower pads. In a plan view, the first and third lower pads may be adjacent to center and edge portions of the substrate, respectively, and the second lower pad may be disposed therebetween. A width of a bottom surface of the second lower pad may be smaller than that of the first lower pad and may be larger than that of the third lower pad.

Layouts for data pads on a semiconductor die are disclosed. An apparatus may include circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The apparatus may also include data pads variously electrically coupled to the circuits. The data pads may include a data pad positioned a first distance from the first edge and a second distance from the second edge. The apparatus may also include dummy data pads electrically isolated from the circuits. The dummy data pads may include a dummy data pad positioned substantially the first distance from the first edge and substantially the second distance from the fourth edge. Associated systems and methods are also disclosed.

A semiconductor device includes a first semiconductor component including a first semiconductor substrate and a first wiring structure, and a second semiconductor component including a second semiconductor substrate and a second wiring structure. A first surface of the first semiconductor component and a second surface of the second semiconductor component are bonded together. Assuming that regions having circumferences respectively corresponding to shapes obtained by vertically projecting the first surface, the second surface, the first wiring structure, and the second wiring structure on a virtual plane are first to fourth regions, respectively, an area of the first region is smaller than an area of the second region, the entire circumference of the first region is included in the second region, an area of the fourth region is smaller than an area of the third region, and the entire circumference of the fourth region is included in the third region.

A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer.

The present application provides a semiconductor structure including a first die, a second die and a first via. The first die includes a first substrate, a first interconnect structure having a first conductive pad, and a first bonding layer over the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second interconnect structure. The first via extends through the second die and the first bonding layer and coupled to the first conductive pad. The first via includes a first portion having a first width and a second portion coupled to the first portion and having a second width different from the first width, wherein the first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

The present application provides a semiconductor structure including a first die, a second die and a first via. The first die includes a first substrate, a first interconnect structure having a first conductive pad, and a first bonding layer over the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second interconnect structure. The first via extends through the second die and the first bonding layer and coupled to the first conductive pad. The first via includes a first portion having a first width and a second portion coupled to the first portion and having a second width different from the first width, wherein the first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

A semiconductor package includes a first semiconductor chip comprising a first semiconductor substrate and a first via electrode passing through at least a portion of the first semiconductor substrate; a second semiconductor chip on the first semiconductor chip and comprising a second semiconductor substrate; a first bonding pad structure between the first semiconductor chip and the second semiconductor chip; a first dummy bonding pad structure between the first semiconductor chip and the second semiconductor chip; and a first inter-chip insulation layer on a surface of the first semiconductor chip, and a second inter-chip insulation layer on a surface of the second semiconductor chip, in which the first bonding pad structure comprises: a first bonding pad on the surface of the first semiconductor chip, and a second bonding pad on the surface of the second semiconductor chip.

A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.