In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, a non-conductive layer aligned with the semiconductor layer, and a contact structure in the non-conductive layer. The non-conductive layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer/second doped layer, but also can improve surface roughness of the first doped layer/second doped layer.

Disclosed is a bonded structure including an element with a bonding surface, the bonding surface having a dielectric region and a first semiconductor region laterally spaced from the dielectric region. The bonded structure further includes a first die directly bonded to the dielectric region of the element without an intervening adhesive. The bonded structure further includes a second die having a second bonding surface having a second semiconductor region, the second semiconductor region being bonded to the first semiconductor region of the element without an intervening adhesive and without an intervening deposited dielectric material.

A semiconductor device including a tapered spacer and method for manufacturing the same are disclosed. The semiconductor device includes a conductive-line contact plug and a conductive pattern spaced apart from each other in a first direction; a conductive line disposed over the conductive-line contact plug and extending in a second direction perpendicular to the first direction; and a spacer structure configured to contact sidewalls of the conductive line and the conductive-line contact plug, and configured such that a width of an upper portion of the spacer structure is narrower than a width of a lower portion of the spacer structure.

A controller applied to a power converter includes a startup and pulse control circuit, a power switch, a startup circuit, and a clamping circuit. The power switch is coupled to a primary side of the power converter and the startup and pulse control circuit, and turned on according to a gate control signal generated by the startup and pulse control circuit. The startup circuit is coupled to the primary side of the power converter, the startup and pulse control circuit and the power switch, and turned on according to a startup signal generated by the startup and pulse control circuit. The clamping circuit is coupled to the startup and pulse control circuit and the power switch, and clamps a current flowing through the startup circuit when the startup circuit is turned on.

A conductor-filled via formed in a staircase structure that is provided in conjunction with a 3-dimensional array of memory strings, where the staircase structure includes multiple steps with each step including a bit line layer and a source line layer. The conductor-filled via includes a conductor to electrically connect a top layer in a first step in the staircase structure to a buried contact provided under the staircase structure, the top layer being the bit line layer or the source line layer of the first step; and a spacer insulator lining the sidewalls of the conductor-filled via to isolate the conductor from at least a bottom layer of the first step and the bit line layer or the source line layer in any steps between the first step and the buried contact.

A semiconductor device of the present disclosure includes a semiconductor substrate having an element formation portion and a composite capacitor formed to surround the element formation portion in plan view. The composite capacitor has a plurality of capacitor elements electrically connected in parallel.

A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

A method of manufacturing an electronic device includes a) forming, in a semiconductor substrate first doped regions of a first type and second doped regions of a second type; b) depositing a dielectric layer on the upper surface of the substrate; c) after step b), forming first and second openings in dielectric layer to expose the first and second regions; d) implanting non-doping ions in the second regions to amorphize an upper portion of the second regions; e) after steps c) and d), filling the first and second openings with doped monocrystalline or polycrystalline silicon of the first type; and f) performing a thermal anneal of the device to recrystallize said upper portion of the second regions and generate crystal defects in a space charge region of a p-n junction formed at the interface between the vias and the second regions.

Semiconductor devices and a method for manufacturing the semiconductor devices are provided. The method includes forming a plurality of bit-line structures on a chip region of a substrate, forming a first alignment key pattern on a scribe line region of the substrate, forming a first alignment key trench in at least a portion of the first alignment key pattern, forming a landing pad layer between the plurality of bit-line structures and on top surfaces of the plurality of bit-line structures, forming a gap-fill layer on the landing pad layer and in an unoccupied portion of the first alignment key trench and performing a planarization process on the gap-fill layer and the landing pad layer.