Patent classifications
H10W72/963
Integrated circuit packages and methods
An integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. The integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. The stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. The stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.
Photoelectric conversion apparatus, photoelectric conversion system, and moving object
A photoelectric conversion apparatus includes a first chip having a first semiconductor element layer including a pixel region of a plurality of pixel circuits, and a second chip having a second semiconductor element layer. The first and second chips are bonded by a plurality of metal bonding portions between the first and second semiconductor element layers. The plurality of metal bonding portions includes first and second metal bonding portions disposed in a region overlapping with the pixel region in a plan view. The first metal bonding portion connects at least either one of the plurality of pixel circuits and the second semiconductor element layer. The second metal bonding portion is connected to at least either one of the plurality of pixel circuits and is not connected to the second semiconductor element layer in the region overlapping with the pixel region.
Semiconductor device structure with bonding pad and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a device region and a seal ring region surrounding the device region. The semiconductor device structure includes a seal ring structure over the seal ring region. The seal ring structure surrounds the device region. The semiconductor device structure includes a bonding film over the seal ring structure and the substrate. The semiconductor device structure includes a bonding pad embedded in the bonding film. The bonding pad overlaps the seal ring structure along an axis perpendicular to a first top surface of the substrate, and a second top surface of the bonding pad is substantially level with a third top surface of the bonding film.
Semiconductor structure having dummy conductive member and manufacturing method thereof
The present application provides a semiconductor structure having a dummy conductive member, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, a first bonding layer over the first dielectric layer, a first via extending through the first bonding layer, and a first dummy conductive member disposed adjacent to the first via and extending partially through the first bonding layer; and a second wafer including a second bonding layer over the first bonding layer, a second via extending through the second bonding layer, a second dummy conductive member disposed adjacent to the second via and extending partially through the second bonding layer, a second dielectric layer over the second bonding layer, and a second substrate over the second dielectric layer.
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method therefor. The structure includes: a first dielectric layer disposed on a substrate, where the first dielectric layer has a first surface away from the substrate; a first bond pad, passing through the first surface and extending to a first depth below the first surface; a second bond pad, passing through the first surface and extending to a second depth below the first surface, where the second depth is less than the first depth; and a second dielectric layer, disposed on the first surface, where a first gap and a second gap are provided in the second dielectric layer, the first gap exposes the top surface of the first bond pad, and the second gap exposes the top surface of the second bond pad.