A semiconductor module includes a heat sink configured to conduct a cooling fluid in a cooling-fluid flow direction. A first semiconductor assembly is arranged on a surface of the heat sink. The first semiconductor assembly includes a first substrate having a first dielectric material layer, and a first semiconductor element connected to the first substrate. A second semiconductor assembly is arranged on the surface of the heat sink and closest to a downstream end of the heat sink. The second semiconductor assembly includes a second substrate having a second dielectric material layer, and a second semiconductor element connected to the second substrate. The second dielectric material layer has a thermal conductivity which is higher than a thermal conductivity of the first dielectric material layer.

A wafer-to-wafer bonding structure includes a first wafer having a first bonding layer thereon, a first main pattern region, a first scribe lane surrounding the first main pattern region, and a first alignment cavity disposed in the first bonding layer within the first main pattern region; and a second wafer having a second bonding layer bonded to the first bonding layer, a second main pattern region, a second scribe lane surrounding the second main pattern region, and a second alignment cavity disposed in the second bonding layer within the second main pattern region.

Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips. Embodiments of the present disclosure may at least simplify the double-sided heat dissipation structure and improve the heat dissipation effect of the chip.

The present specification provides a display device using semiconductor light-emitting diodes which are self-assembled in fluid, and a method for manufacturing same. Specifically, the semiconductor light-emitting diode comprises: a first-conductive-type electrode layer and a second-conductive-type electrode layer; a first-conductive-type semiconductor layer electrically connected to the first-conductive-type electrode layer; an active layer provided on the first-conductive-type semiconductor layer; and a second-conductive-type semiconductor layer provided on the active layer and electrically connected to the second-conductive-type electrode layer, wherein one surface of the second-conductive-type semiconductor layer comprises a mesa structure formed by etching a portion of the one surface, and the second-conductive-type electrode layer is provided on the one surface comprising the mesa structure of the second-conductive-type semiconductor layer.

A copper paste for joining contains metal particles and a dispersion medium, in which the copper paste for joining contains copper particles as the metal particles, and the copper paste for joining contains dihydroterpineol as the dispersion medium. A method for manufacturing a joined body is a method for manufacturing a joined body which includes a first member, a second member, and a joining portion that joins the first member and the second member, the method including: a first step of printing the above-described copper paste for joining to at least one joining surface of the first member and the second member to prepare a laminate having a laminate structure in which the first member, the copper paste for joining, and the second member are laminated in this order; and a second step of sintering the copper paste for joining of the laminate.

A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

A method of manufacturing a semiconductor device includes reducing a thickness of a device wafer bonded to a carrier wafer, wherein the device wafer includes a device, a portion of the carrier wafer beyond the device, in a plan view, is called a non-bonding area, and a portion of the carrier wafer overlapping the device, in the plan view, is called a device area. The method further includes performing an etching process on the non-bonding area of the carrier wafer, wherein the etching process is performed completely outside the device area of the carrier wafer.

A temporary fixing composition contains an organic component in a proportion of 42 mass % or more and 95 mass % or less. The organic component is solid at 25 C. and has a 95% mass loss temperature in nitrogen of 300 C. or lower. The temporary fixing composition is used to temporarily fix a first bonding target material and a second bonding target material to each other before the two bonding target materials are bonded to each other. A method for producing a bonded structure of the present invention includes temporarily fixing a first bonding target material and a second bonding target material to each other with the temporary fixing composition disposed therebetween and firing the temporarily fixed two bonding target materials to bond the two bonding target materials to each other.

In an embodiment of the present inventive concept, a high bandwidth memory includes a base die, and a semiconductor stack disposed on the base die, the semiconductor stack comprising a plurality of underfill members and a plurality of memory dies that are alternately stacked. Each of the plurality of underfill members includes first sides, each of the plurality of memory dies includes second sides, and each of the first sides is recessed from a corresponding second side.

Disclosed are architectures of semiconductor integrated circuit (IC) device. The semiconductor IC device includes a unified logic die and a memory array die heterogeneously integrated with the unified logic die. The unified logic die includes a compute logic block and a memory the memory logic block monolithically integrated with the compute logic block die on a same substrate. The memory logic block includes a memory peripheral circuitry configured for controlling a memory cell array external to the unified logic die. The memory array die includes the memory cell array, and the memory array die is communicatively coupled with the memory logic block.