A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

A semiconductor package includes: a base chip; semiconductor chips disposed on the base chip and including front pads disposed on a front surface opposing the base chip, rear pads disposed on a rear surface opposing the front surface, and through-vias; bumps disposed between the semiconductor chips; a dam structure disposed on at least a portion of the rear pads; and insulating adhesive layers at least partially surrounding the bumps and the dam structure, wherein the rear pads include first pads that are disposed in a center region that crosses a center of the rear surface and that are electrically connected to the through-vias, and second pads that are disposed in a peripheral region adjacent to the center region, wherein the second pads include a line pad of which at least a portion has a polygonal shape, and wherein the dam structure has a bent shape.

A method of fabricating an electronic device including fabricating a multilevel package substrate with first, second, third, and fourth levels, a semiconductor die mounted to the first level, and fabricating a conductor backed coplanar waveguide transmission line feed with an interconnect and a conductor, the interconnect including coplanar first, second, and third conductive lines extending in the first level along a first direction from respective ends to an antenna, the second and third conductive lines spaced apart from opposite sides of the first conductive line along an orthogonal second direction, and the conductor extending in the third level under the interconnect and under the antenna.

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region.

An image sensor includes a stack structure including an active pixel region of pixels, and a pad region. The stack structure further includes a first substrate including a photoelectric conversion region and a floating diffusion region, a first semiconductor substrate, a first front structure arranged on a first surface of the first semiconductor substrate, a second substrate attached to the first front structure and including pixel gates, a second semiconductor substrate, and a second front structure, a third substrate attached to the second substrate and including a logic transistor for driving the pixels, and a pad arranged in the pad region. A side surface and a bottom surface of the pad are surrounded by the second front structure, and at least a portion of a top surface of the pad is exposed through a pad opening penetrating the first substrate and extending into the second substrate.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.

A semiconductor device including a transistor region including vertical transistors arranged in an array to form a memory array area, and word lines connected to the vertical transistors. A capacitor region is formed within the memory array area above the transistor region and including vertical capacitors vertically connected to the vertical transistors through capacitor contacts. Bit lines are formed below the transistor region and vertically connected to the vertical transistors, the word lines and bit lines being arranged to form a matrix configuration within the memory array area. Backside contacts are formed within the memory array area, each backside contact connected to either a respective word line or a respective bit line and extending vertically to below the bit lines.

A semiconductor package includes a flexible circuit board and a chip which includes a first bump group and a second bump group. First bumps of the first bump group and second bumps of the second bump group are provided to be bonded to leads on the flexible circuit board. The second bumps are designed to be longer than the first bumps in length so as to increase bonding strength of the second bumps to the leads, prevent the leads from being shifted and separated from the first and second bumps and prevent lead bonding misalignment.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a first upper pad arranged on an upper surface of the first semiconductor substrate, a first polymer layer arranged on the upper surface of the first semiconductor substrate, a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second lower pad arranged under a lower surface of the second semiconductor substrate, wherein the first polymer layer has a horizontal width in a direction crossing the first polymer layer in a center region of the second semiconductor chip, as a first length, and has a horizontal width in a direction crossing two corner regions of the first polymer layer in corner regions of the second semiconductor chip, as a second length, wherein the second length is greater than the first length.