Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

A semiconductor package includes a substrate with electrical conductors, one or more semiconductor dies disposed on the substrate and electrically connected with the electrical conductors of the substrate, and a lid disposed on the substrate. The one or more semiconductor dies are disposed in a space enclosed by the substrate and the lid. At least one thermoelectric device is at least partly embedded in the lid. The at least one thermoelectric device may be operated to cool the semiconductor package, or to heat the semiconductor package. A controller for the at least one thermoelectric device may be implemented in the one or more semiconductor dies.

Provided is a chip stack structure including a passivation layer, a plurality of conductive pillars passing through the passivation layer, a buffer chip located on the passivation layer, a plurality of core chips located on the buffer chip and stacked in a vertical direction, and a first molding layer located on the passivation layer and surrounding the buffer chip and the plurality of core chips, wherein an area of an upper surface of the passivation layer is greater than an area of a lower surface of the buffer chip.

Methods, apparatuses, and systems related to a memory controller on an interface die and outside of a processor are described. Operations of the memory controller may be further facilitated by a circuit interface fabric configured to utilize separate write and read data buses within the interface die.

A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least four electronic circuit units (ECUs), where each of the ECUs include a first circuit, the first circuit including a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One stacked die platform includes a substrate, a first die and a second die stacked together, and first and C2C interfaces on the first and second dies, respectively. The stacked die platform also includes switching circuitry and a link monitoring unit. The switching circuitry is configured to selectively connect either the first C2C interface or the second C2C interface to the bump connections, where only one of the first C2C interface and the second C2C interface is active at a time. The link monitoring unit is configured to monitor link status and control operation of the switching circuitry to provide redundancy for C2C communication failures.

Examples of the present application provide a semiconductor structure and a fabrication method thereof, relate to the field of semiconductor chip technologies, and aim to stack more device layers in a semiconductor structure and in turn increase the number of the device layers packaged in the semiconductor structure. The semiconductor structure provided by an example of the present application includes a plurality of stack layers that are stacked and a first bonding structure, wherein two adjacent stack layers are connected together through the first bonding structure; the stack layer includes a plurality of device layers that are stacked and a second bonding structure with two adjacent device layers connected through the second bonding structure. After connecting device layers together through the second bonding structure, the thickness of the device layers can be reduced.

Disclosed herein are related to a device comprising a memory chip, another memory chip, and a circuit chip between the memory chip and the another memory chip, where the circuit chip is connected to the memory chip and the another memory chip through different connections. The memory chip may include a first memory array and a first bond pad, and the another memory chip may include a second memory array and a second bond pad. The circuit chip may include a third bond pad on a first surface of the circuit chip coupled to the first bond pad, and a fourth bond pad on a second surface of the circuit chip coupled to the second bond pad. The circuit chip may include a transistor coupled to the third bond pad through a front side connection and another transistor coupled to the fourth bond pad through a backside connection.