A device may include a plurality of chiplets stacked on top of each other. Each chiplet includes a central region and an edge region outside the central region; one or more electronic components disposed within the central region; and a plurality of through-chiplet vias extending through the chiplet. The plurality of through-chiplet vias are disposed in the edge region. The device may further include a coil including a plurality of turns formed in at least two chiplets of the plurality of chiplets. Each turn includes at least two through-chiplet vias of at least one chiplet of the plurality of chiplets. The through-chiplet vias of the plurality of through-chiplet vias of the at least two turns of the plurality of turns of the coil are formed in a common plane perpendicular to main surfaces of the plurality of chiplets.

A semiconductor package may include: a first double-chip structure including a first semiconductor chip, a second semiconductor chip, a first scribe lane region dividing the first semiconductor chip and the second semiconductor chip, and a first through hole in the first scribe lane region; a second double-chip structure on the first double-chip structure, the second double-chip structure including a third semiconductor chip, a fourth semiconductor chip, a second scribe lane region dividing the third semiconductor chip and the fourth semiconductor chip, and a second through hole in the second scribe lane region; first conductive connection members between the first and second double-chip structures and configured to electrically connect the first and third semiconductor chips and the second and fourth semiconductor chips; and a molding member on the first double-chip structure and the second double-chip structure and in the first through hole and the second through hole.

A semiconductor package includes a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip, a first bonding layer structure between the second semiconductor chips and including a first bonding pad structure, and a filling pattern contacting at least a portion of each of the second semiconductor chips and including silicon oxide or polymer. A sidewall of the filling pattern is aligned with a sidewall of the first semiconductor chip in the vertical direction. The first bonding layer structure includes first and second bonding layers contacting each other. The first bonding pad structure includes first and second bonding pads in the first and second bonding layers, respectively, and contacting each other. The first bonding layer contacts an upper surface of a lower one of the second semiconductor chips. The second bonding layer contacts a lower surface of an upper one of the second semiconductor chips.

Layouts for data pads on a semiconductor die are disclosed. An apparatus may include circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The apparatus may also include data pads variously electrically coupled to the circuits. The data pads may include a data pad positioned a first distance from the first edge and a second distance from the second edge. The apparatus may also include dummy data pads electrically isolated from the circuits. The dummy data pads may include a dummy data pad positioned substantially the first distance from the first edge and substantially the second distance from the fourth edge. Associated systems and methods are also disclosed.

A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.

Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.

A semiconductor device includes backside power rails over a bulk semiconductor material, a first bonding dielectric layer over the backside power rails, a first tier of transistors over the first bonding dielectric layer, a second bonding dielectric layer over the first tier of transistors, and a second tier of transistors over the second bonding dielectric layer. The first tier of transistors includes first channel structures having a first epitaxially grown semiconductor material. The second tier of transistors includes second channel structures having a second epitaxially grown semiconductor material. The backside power rails are spaced apart from the first tier of transistors by the first bonding dielectric layer. The first tier of transistors is spaced apart from the second tier of transistors by the second bonding dielectric layer.