A chip package structure includes a die pad, input/output pads, a chip, first bonding wires, a molding compound, a solder resist layer, first solder balls and second solder balls. The input/output pads are configured around the die pad. The chip is configured on the die pad. The first bonding wires are electrically connected to the chip and the input/output pads. The molding compound covers the chip, the die pad, the input/output pads and the first bonding wires, and exposes a first lower surface of the die pad and a second lower surface of each input/output pad. The solder resist layer is configured on the first lower surface of the die pad and has multiple openings exposing a portion of the die pad. The first solder balls are respectively configured in the openings of the solder resist layer, and the second solder balls are respectively configured on the input/output pads.

A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer, and a connection member bonded to the under bump.

Embodiments provide a method of manufacturing a semiconductor device, including forming two grooves that extend from a first surface of a semiconductor wafer along a dicing region of the semiconductor wafer and are arranged side by side, the semiconductor wafer including the first surface and a second surface opposite to the first surface. The manufacturing method includes irradiating between the two grooves from the second surface of the semiconductor wafer with a first laser beam when viewed from above to form a modified portion in the semiconductor wafer along the dicing region. The manufacturing method includes cleaving the semiconductor wafer to segment the semiconductor wafer into a plurality of semiconductor chips.