A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

A semiconductor package includes at least a first die. The first die includes an internal circuit disposed on a substrate, an electrostatic discharge (ESD) protection circuit disposed on the substrate but laterally spaced from the internal circuit and including a first charge dissipation element, and a first Silicon Controlled Rectifier (SCR) laterally adjacent to and spaced from the first charge dissipation element.

A package structure includes a first dielectric layer disposed on a first patterned circuit layer, a first conductive via in the first dielectric layer and electrically connected to the first patterned circuit layer, a circuit layer on the first dielectric layer, a second dielectric layer on the first dielectric layer and covering the circuit layer, a second patterned circuit layer on the second dielectric layer and including conductive features, a chip on the conductive features, and a molding layer disposed on the second dielectric layer and encapsulating the chip. The circuit layer includes a plurality of portions separated from each other and including a first portion and a second portion. The number of pads corresponding to the first portion is different from that of pads corresponding to the second portion. An orthographic projection of each portion overlaps orthographic projections of at least two of the conductive features.

Disclosed circuit arrangements include a physically unclonable function (PUF) entropy source having passive circuit elements and active circuit elements. A first die has one or more metal layers and an active layer, and the passive circuit elements are disposed in the one or more metal layers. A second die has one or more metal layers and an active layer. The active circuit elements are coupled to the passive circuit elements and are disposed in the active layer of the second die, and the first die and the second die are in a stacked structure. The stacked structure has the one or more metal layers of the first die disposed between the active layer of the first die and the active layer of the second die.

Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

A semiconductor package, includes: a first semiconductor chip including first connection pads on the first front surface, and through electrodes extending perpendicularly to the first rear surface and electrically connected to at least a portion of the first connection pads; a second semiconductor chip including second connection pads on the second front surface, and on the first rear surface so that the second rear surface faces the first semiconductor chip; a dielectric layer on the second semiconductor chip; first conductive structures in the dielectric layer, and connecting the through electrodes of a first group and the second connection pads; second conductive structures in the dielectric layer, and having first and second ends, the first ends connected to the through electrodes of a second group and at least a portion of the second ends thereof being exposed from the dielectric layer; at least one third semiconductor chip including third connection pads on the third front surface, and on the dielectric layer so that the third rear surface faces the second semiconductor chip; conductive wires connecting the second conductive structures and the third connection pads.

A semiconductor device includes a first die including a first stack of layers in a first region on a backside of the first die and a second stack of layers in a second region on the backside of the first die. The first stack of layers has a smaller number of different layers than the second stack of layers. A contact structure is formed in the first region on the backside of the first die. The contact structure extends through the first stack of layers and is configured to conductively connect a first conductive structure on a face side of the first die with a second conductive structure on the backside of the first die. The face side is opposite to the backside.

Various aspects of the present disclosure generally relate to a bonding pad configuration. A device includes a die including multiple bonding pads, pad configuration circuitry, and control circuitry. The pad configuration circuitry is configured to, based on a routing configuration, selectively connect multiple nodes of first circuitry to a first set of bonding pads of the multiple bonding pads. The control circuitry is connected to the pad configuration circuitry and configured to obtain the routing configuration.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.