A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a device region and a seal ring region surrounding the device region. The semiconductor device structure includes a seal ring structure over the seal ring region. The seal ring structure surrounds the device region. The semiconductor device structure includes a bonding film over the seal ring structure and the substrate. The semiconductor device structure includes a bonding pad embedded in the bonding film. The bonding pad overlaps the seal ring structure along an axis perpendicular to a first top surface of the substrate, and a second top surface of the bonding pad is substantially level with a third top surface of the bonding film.

A method includes forming a conductive pad over a substrate, forming a multi-layer passivation structure on the conducive pad, patterning a top portion of the multi-layer passivation structure to form a first opening, forming a mask film on sidewall surfaces of the patterned top portion of the multi-layer passivation structure, after the forming of the mask film, performing a first etching process to remove a portion of the multi-layer passivation structure directly under the first opening to form a second opening, after the performing of the first etching process, selectively removing the mask film, performing a second etching process to remove a portion of the multi-layer passivation structure directly under the second opening, thereby forming a third opening exposing the conductive pad, and forming a bonding structure in the third opening, where an etchant of the second etching process is different than an etchant of the first etching process.

A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.

A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.

A semiconductor package comprises: a first substrate; a first pad on a top surface of the first substrate; a first conductive pattern on a bottom surface of the first pad; and a semiconductor chip on the top surface of the first substrate, wherein the semiconductor chip comprises: a semiconductor substrate; an interconnection layer on a bottom surface of the semiconductor substrate, the interconnection layer comprising an interconnection pattern; and a bonding pad on a bottom surface of the interconnection pattern, wherein the bonding pad is directly bonded to the first pad, wherein a width of the interconnection pattern is larger than a width of the bonding pad, wherein a width of the first conductive pattern is smaller than a width of the first pad, and wherein the interconnection pattern and the bonding pad comprise different materials.

The semiconductor device may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. Each lower pad may be provided such that a width of a top surface thereof is smaller than a width of a bottom surface thereof. The lower pads may include first, second, and third lower pads. In a plan view, the first and third lower pads may be adjacent to center and edge portions of the substrate, respectively, and the second lower pad may be disposed therebetween. A width of a bottom surface of the second lower pad may be smaller than that of the first lower pad and may be larger than that of the third lower pad.