Patent classifications
H10W72/07332
SEMICONDUCTOR PACKAGE
A semiconductor package may include a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip in a vertical direction, adhesive layers interposed between the first semiconductor chip and one of the second semiconductor chips and between the second semiconductor chips, and a molding member on the first semiconductor chip. Edges of the adhesive layers may be positioned inward from sidewalls of the second semiconductor chips. The molding member may cover at least sidewalls of the second semiconductor chips and sidewalls of the adhesive layers. The molding member may fill edge gaps defined by the sidewalls of the adhesive layers and edges of upper surfaces and lower surfaces of the second semiconductor chips.
Manufacturing apparatus and manufacturing method of semiconductor device
A manufacturing apparatus of a semiconductor device includes: a stage; a bonding head, including a mounting tool, a tool heater, and a lifting and lowering mechanism; and a controller performing bonding processing. The controller performs, in the bonding processing: first processing in which, after a chip is brought into contact with a substrate, as heating of the chip is started, the chip is pressurized against the substrate; distortion elimination processing in which, after the first processing and before melting of a bump, the lifting and lowering mechanism is driven in a lifting direction, thereby eliminating distortion of the bonding head; and second processing in which, after the distortion elimination processing, position control is performed on the lifting and lowering mechanism so as to cancel thermal expansion and contraction of the bonding head, thereby maintaining a gap amount at a specified target value.
Display apparatus having display module and manufacturing method thereof
A display module includes: a substrate including a mounting surface on which a plurality of inorganic light-emitting devices are mounted, a side surface, and a rear surface being opposite to the mounting surface; a front cover bonded with the mounting surface and covering the mounting surface; a metal plate bonded with the rear surface; a side cover surrounding the side surface; and a side end member covering at least one portion of a side end of the side cover, and including a first portion being in contact with and grounded to the metal plate and a second portion connected to the first portion and positioned on the side end of the side cover.
Display device using micro-LEDs and method for manufacturing same
The present specification provides a display device using semiconductor light-emitting diodes which are self-assembled in fluid, and a method for manufacturing same. Specifically, the semiconductor light-emitting diode comprises: a first-conductive-type electrode layer and a second-conductive-type electrode layer; a first-conductive-type semiconductor layer electrically connected to the first-conductive-type electrode layer; an active layer provided on the first-conductive-type semiconductor layer; and a second-conductive-type semiconductor layer provided on the active layer and electrically connected to the second-conductive-type electrode layer, wherein one surface of the second-conductive-type semiconductor layer comprises a mesa structure formed by etching a portion of the one surface, and the second-conductive-type electrode layer is provided on the one surface comprising the mesa structure of the second-conductive-type semiconductor layer.
Dam for three-dimensional integrated circuit
An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.
Packaged electronic devices having transient liquid phase solder joints and methods of forming same
A packaged electronic device comprises a power semiconductor die that includes a first terminal and a second terminal, a power substrate comprising a dielectric substrate having a first metal cladding layer on an upper surface thereof, an encapsulation covering the power semiconductor die and at least a portion of the power substrate, a first lead extending through the encapsulation that is electrically connected to the first terminal, and a second lead extending through the encapsulation that is electrically connected to the second terminal. The first terminal is bonded to the first lead via a first transient liquid phase solder joint.
SEMICONDUCTOR PACKAGE
A semiconductor package may include a first semiconductor chip extending in a horizontal direction, a first chip stack and a second chip stack, on the first semiconductor chip and horizontally spaced apart from each other, a supporting structure on the first semiconductor chip and interposed between the first and second chip stacks, a first adhesive layer disposed on the first semiconductor chip in contact with the first chip stack and the supporting structure, and a second adhesive layer disposed on the first semiconductor chip in contact with the second chip stack and the supporting structure. Each of the first and second chip stacks may include second semiconductor chips stacked in a vertical direction. Each of the first and second semiconductor chips may include a penetration via. The first and second adhesive layers may be spaced apart from each other with the supporting structure interposed therebetween.
Silver nanoparticles synthesis method for low temperature and pressure sintering
The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.
Sintering paste and use thereof for connecting components
The invention relates to a sintering paste consisting of: (A) 30 to 40 wt. % of silver flakes with an average particle size ranging from 1 to 20 m, (B) 8 to 20 wt. % of silver particles with an average particle size ranging from 20 to 100 nm, (C) 30 to 45 wt. % of silver(I) oxide particles, (D) 12 to 20 wt. % of at least one organic solvent, (E) 0 to 1 wt. % of at least one polymer binder, and (F) 0 to 0.5 wt. % of at least one additive differing from constituents (A) to (E).
PACKAGING DEVICES AND METHODS FOR FORMING THE SAME
A packaging device is provided. The packaging device includes a die disposed over a laminate, the die comprising a first via structure, and an interposer disposed between the die and the laminate. The interposer includes a second via structure. The packaging device also includes a lid disposed over the interposer and covering the die, a first patterned conductive layer disposed between the die and the interposer, and between the lid and the interposer; and a second patterned conductive layer disposed between the laminate and the interposer. The first patterned conductive layer includes a bonding structure electrically and thermally connected to the first via structure and the second via structure.