An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.

A semiconductor device comprises a semiconductor layer structure that comprises a drift layer having a first conductivity type, a first well region having a second conductivity type, a second well region having the second conductivity type and a JFET region having the first conductivity type, where the JFET region has a doping concentration that is higher than a doping concentration of the drift layer. A gate trench is provided in the semiconductor layer structure. The first well region forms a first sidewall of the gate trench and the second well region forms a second sidewall of the gate trench. Additionally, first and second sidewalls of the JFET region are aligned with respective first and second sidewalls of the gate trench.

A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The first semiconductor material is substantially defect-free silicon carbide, and the second semiconductor material is silicon. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.

The disclosure provides dyes for marking hydrocarbon compositions. More particularly, the disclosure relates to non-mutagenic dyes for marking hydrocarbon compositions.

An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

A method of manufacturing semiconductor devices includes processing a semiconductor body at a first surface of the semiconductor body, including forming a wiring area over the first surface. Thereafter, the method further includes forming a field stop region in the semiconductor body. Forming the field stop region includes introducing implant ions including selenium into the semiconductor body through a second (opposite) surface of the semiconductor body by an ion implantation process. A main beam direction of the ion implantation process deviates from a main crystal direction of the semiconductor body, along which channeling of implant ions occurs, by at most 1 degree and a main beam incidence angle divergence is at most 0.5 degree. Forming the field stop region further includes electrically activating at least part of the selenium by a laser annealing process.

The SiC semiconductor device includes: a semiconductor substrate containing SiC; an insulated gate electrode structure buried in a first trench 8 provided in the semiconductor substrate; a trench contact 12 buried in a second trench 11 provided in the semiconductor substrate; a second conductivity type base region provided in contact with a side surface of the first trench and a side surface of the second trench in the semiconductor substrate; a first conductivity type main electrode region provided in contact with the side surface of the first trench and the side surface of the second trench on an upper surface side of the base region; and a second conductivity type base contact region provided in contact with a bottom surface of the second trench, in which a region along the side surface and the bottom surface of the second trench in the semiconductor substrate contains 3H-SiC.

A semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The first doped region is in the drift region and between the drain region and the gate structure. The second doped region is within the drift region. The second doped region forms a P-N junction with the first doped region at a bottom surface of the first doped region.

The present disclosure describes a system and a method for an ion implantation (IMP) process. The system includes an ion implanter configured to scan an ion beam over a target for a range of angles, a tilting mechanism configured to support and tilt the target, an ion-collecting device configured to collect a distribution and a number of ejected ions from the ion beam scan over the target, and a control unit configured to adjust a tilt angle based on a correction angle determined based on the distribution and number of ejected ions.

A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. A polysilicon material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A conductive layer is formed over the semiconductor layer. The polysilicon material is coupled to the conductive layer and operates as a field plate. A first insulating layer is formed between the polysilicon material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region.