Semiconductor devices and processes for manufacturing semiconductors are described. A semiconductor device can include a drift region formed on a Silicon Carbide substrate. The semiconductor device can include a trench that penetrates through a source region and a channel and reaches the drift region. The semiconductor device can include an oxide region lining the trench. The oxide region can include a bottom portion, a lower side portion and an upper side portion. A thickness of the bottom portion and a thickness of the lower side portion can be greater than a thickness of the upper side portion. The semiconductor device can include a gate electrode formed in the trench lined with the oxide region. The semiconductor device can include a shield region in contact with a bottom portion of the trench. A width of the semiconductor region can be less than or equal to a width of the trench.

A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type. The semiconductor structure further includes a drift layer of the first conductivity type located above the semiconductor substrate, a channel layer of a second conductivity type located above the drift layer, and a source region of the first conductivity type located above the channel layer. The second conductivity type is opposite to the first conductivity type. A plurality of trenches penetrates through the source region, the channel layer and a portion of the drift region. A gate electrode is located within each of the plurality of trenches via a gate insulating film and a plurality of shielding structures of the second conductivity type is located around the gate electrode. The plurality of shielding structures covers sidewalls and a bottom of the plurality of trenches. The plurality of shielding structures is arranged in an island-like manner.

Methods for fabricating SiC MOSFETs using compensating ion implants are disclosed. An n-type silicon carbide layer is epitaxially grown. After this growth process, a compensating ion implantation process is performed. This ion implantation process is used to compensate for the known dopant non-uniformity in the n-type silicon carbide layer. After the dopant concentration has been compensated, the traditional processes used to fabricate a planar SiC MOSFET may be performed. For super junction MOSFETs, the n-type epitaxial growth and compensating ion implantation processes may be repeated a plurality of times.

An embodiment relates to a method obtaining a silicon carbide wafer comprising a first conductivity type substrate and a first conductivity type drift layer, forming a second conductivity type first well region within the first conductivity type drift layer, forming a first conductivity type source region within the second conductivity type first well region, forming a second conductivity type plug region under the first conductivity type source region, forming a gate oxide layer, forming a patterned gate metal layer, depositing an interlevel dielectric (ILD) layer, forming a first patterned mask layer on top of the ILD layer, and etching the ILD layer and the first conductivity type source region using the first patterned mask layer, and forming a silicide layer, wherein the silicide layer is in contact with a vertical sidewall of the first conductivity type source region and at-least one second conductivity type region.

Provided is a method of forming a thin film to minimize an increase in defects at an interface during a high-temperature oxidation process of a SiC substrate. The method includes depositing a first thin film on the SiC substrate by applying a radical gas, forming an oxide film on the first thin film by performing the high-temperature oxidation process, and performing annealing on the oxide film.

A method of manufacturing a silicon carbide semiconductor device includes formation of an electrode and formation of a gate wiring. The electrode is formed to be electrically connected to a base layer and an impurity region included in a semiconductor substrate through a first contact hole. The gate wiring is formed to be electrically connected to a connection wiring through a second contact hole, and is made of material capable of deoxidizing an oxide film. The oxide film is removed by deoxidizing the oxide film formed on the connection wiring to remove the oxygen from the oxide film into the gate wiring through heating treatment for the gate wiring in the formation of the gate wiring or after the formation of the gate wiring.