A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.

A wafer includes a buried substrate; a layer of silicon (100) disposed on the buried substrate and forming multiple U-shaped grooves, wherein each U-shaped groove comprises a bottom portion and silicon sidewalls (111) at an angle to the buried substrate; a buffer layer disposed within the multiple U-shaped grooves; and multiple gallium nitride (GaN)-based structures having vertical sidewalls disposed within and protruding above the multiple U-shaped grooves, the multiple GaN-based structures each including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111).

Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

A method for forming a semiconductor structure includes providing a base with a first area and a second area; patterning a first core material layer and forming first core layers; forming first spacers; patterning a second core material layer and forming second core layers; modifying the second core layers exposed in the second area to form third core layers having an etching selectivity ratio with remaining second core layers; forming second spacers covering sidewalls of the second core layers and third core layers; and patterning a target material layer using the second spacers and third core layers as a mask and forming first target structures and second target structures. The pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures. SAQP and SALELE processes are integrated. Redundant first target structures made by SAQP are removed without adding masks and process steps.

Provided is a semiconductor processing solution containing the following (A) to (E): (A) a quaternary ammonium ion represented by formula (1); (B) a halide ion; (C) a hydroxide ion; (D) an oxidizer, and (E) water. (In the formula, R.sup.1, R.sup.2, R.sup.3, and R.sup.4 are each independently a C1-16 alkyl group, provided that the number of carbon atoms in at least one alkyl group among R.sup.1, R.sup.2, R.sup.3, and R.sup.4 is 2-16.)

A method is provided for manufacturing a semiconductor structure. The method includes providing a through hole penetrating a stacked layer and exposing a surface of an interconnecting conductive layer; forming a side wall material layer covering at least a side wall and a bottom of the through hole; forming a protective material layer covering the side wall material layer; performing thermal processing on the protective material layer, to cause the protective material layer to implement a material phase change process; etching and removing materials located at the bottom of the through hole to expose the surface of the interconnecting conductive layer, covering the side wall of the through hole, of the side wall material layer as a side wall layer, and taking a remaining protective material layer covering the side wall layer as a protective layer. Working performance of the semiconductor structure is improved.