A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

A semiconductor device includes a substrate having a first main surface and a second main surface opposite to the first main surface, and a first conductive layer including a first metal layer and a second metal layer, the first metal layer covering the second main surface, the second metal layer covering the first metal layer and including dendrites, wherein a via hole extending through the substrate and having an inner wall surface is formed in the substrate, and wherein the first metal layer, which is covered with the second metal layer, covers the inner wall surface.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

Bonded die structures and methods of fabrication thereof that provide reduced defects and higher reliability. A laser grooving process may be used to precut bonded device structures prior to a final dicing process. The laser grooving process may form relatively deep grooves in the bonded device structure that may extend beyond the bonding interface between a first device structure and a second device structure. A final dicing process along the precut grooves may be used to separate individual bonded die structures. Because the dicing occurs along the deep precut grooves that extend through the bonding interface between the stacked device structures, the dicing blade may not cut through or come into contact with the bonding interface. This may result in in reduced mechanical stress, which may decrease the occurrence of delamination defects between the device structures and thereby provide improved reliability and increased yields.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

A device comprising a memory device comprising: a first memory chip; a second memory chip coupled to the first memory chip, wherein a front side of the first memory chip is coupled to a front side of the second memory chip; a third memory chip coupled to the second memory chip, wherein a back side of the second memory chip is coupled to a back side of the third memory chip through fusion bonding; and a fourth memory chip coupled to the third memory chip, wherein a front side of the third memory chip is coupled to a front side of the fourth memory chip.

A device comprising a memory device comprising: a first memory chip; a second memory chip coupled to the first memory chip, wherein a front side of the first memory chip is coupled to a front side of the second memory chip; a third memory chip coupled to the second memory chip, wherein a back side of the second memory chip is coupled to a back side of the third memory chip through hybrid bonding; and a fourth memory chip coupled to the third memory chip, wherein a front side of the third memory chip is coupled to a front side of the fourth memory chip.