A method of forming an integrated circuit (IC) is provided. The method includes forming a seed layer of a first metal material over a circuit on a device side of a semiconductor die. The method also includes forming a multi-layer conductive contact on the seed layer. The multi-layer conductive contact has a width in a first dimension and includes a plurality of layers of different metal materials and a portion of the seed layer extends outwardly from a periphery of the multi-layer conductive contact. The method further includes forming a sacrificial layer of the first metal material over the multi-layer conductive contact. The method yet further includes etching to remove the seed layer and the sacrificial layer.

A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

A bonding pad structure and a method of manufacturing a bonding pad structure are provided. The bonding pad structure includes a carrier, a first conductive layer disposed over the carrier, a second conductive layer disposed on the first conductive layer and contacting the first conductive layer, and a third conductive layer disposed on the second conductive layer and contacting the second conductive layer. The bonding pad structure also includes a first passivation layer disposed on the first conductive layer and contacting at least one of the first conductive layer or the second conductive layer. An upper surface of the third conductive layer facing away from the carrier is exposed from the first passivation layer.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

An electronic system includes a first device and a second device bonded to the first device. The first device includes: a semiconductor substrate with an opening; a stack having metal layers and conductive vias; and a conductive layer including aluminum having a first face in contact with the stack and a second face, opposite the first face, that is partially exposed through the opening. The metal layers and the conductive vias of the stack are made of a conductive material different from aluminum.

A fan-out semiconductor package includes a semiconductor chip; a metal pillar disposed on the semiconductor chip; a bonding metal layer disposed on the metal pillar; a bonding wire disposed on the bonding metal layer; a sealing layer over the semiconductor chip, and surrounding the metal pillar, the bonding metal layer, and the bonding wire; and a redistribution layer disposed on the sealing layer and the bonding wire.

A semiconductor device including a transistor region including vertical transistors arranged in an array to form a memory array area, and word lines connected to the vertical transistors. A capacitor region is formed within the memory array area above the transistor region and including vertical capacitors vertically connected to the vertical transistors through capacitor contacts. Bit lines are formed below the transistor region and vertically connected to the vertical transistors, the word lines and bit lines being arranged to form a matrix configuration within the memory array area. Backside contacts are formed within the memory array area, each backside contact connected to either a respective word line or a respective bit line and extending vertically to below the bit lines.

A semiconductor device according to some embodiments includes a semiconductor die, and a bond pad on a first side of the semiconductor die for receiving a wire bond. The bond pad includes a discontinuous uppermost surface opposite the first side of the semiconductor die.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.