H10W40/611

MEMORY DEVICE
20260114280 · 2026-04-23 · ·

A memory device includes a first case, a second case coupled to the first case, a mid plate placed in an inner space between the first and second cases, a first memory module between the first case and the mid plate, including a first module substrate and at least one first electronic chip on the first module substrate, and a second memory module between the second case and the mid plate, including a second module substrate and at least one second electronic chip on the second module substrate, wherein the mid plate includes a base unit, a first rib structure extending from the base unit to electrically connect the mid plate to the first module substrate, and a second rib structure spaced apart from the first rib structure to electrically connect the mid plate to the first module substrate.

SYSTEMS AND METHODS FOR LOW INDUCTANCE PHASE SWITCH FOR INVERTER FOR ELECTRIC VEHICLE

A system includes: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a power module including: a first phase switch including one or more first phase power switches on a first side of a substrate; and a second phase switch including one or more second phase power switches on a second side of the substrate opposite to the first side.

BACK SIDE POWER DELIVERY FOR WAFER-SCALE INTEGRATION WITH AN ISOMETRIC GRID ARRAY WITH COMPRESSION PINS

Disclosed techniques enable provide techniques for improved power delivery for wafer-scale integration. A wafer-scale integration interposer (WSII) is accessed. A front side of the WSII is bonded to a plurality of chiplets. The WSII includes through-silicon vias (TSVs).

Modular power substrates (MPSs) are inserted into an isometric grid array (IGA). A back side of the IGA includes a plurality of external compression pins. The MPSs are coupled to the chiplets. The coupling includes compressing, by one or more compression plates, one or more elastomer sheets between the MPSs and the TSVs. The compressing is based on the external compression pins. The MPSs are coupled to DC-to-DC power converters. The coupling is based on sockets. DC power is sent by the DC-to-DC power converters to the chiplets. The sending is based on the MPSs, the one or more elastomer sheets, and the TSVs.

COLD PLATE COOLING FOR WAFER-SCALE INTEGRATION WITH BACK SIDE MODULAR POWER DELIVERY

Techniques for cooling are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The chips create heat during operation. The WSSI includes a plurality of through-silicon vias (TSVs). A back side of the WSSI is coupled to a plurality of DC-to-DC power converters. A cold plate is attached to the chips. The cold plate comprises an inlet plate, a jet-plate, and a fin-plate. A coolant at a first temperature is sent into at least one inlet plate inlet nozzle. The sending includes spraying the coolant on the fin-plate. At least a portion of the heat that was created, by the cold plate, is transferred to the coolant. The coolant is captured, at a second temperature, from one or more outlet chambers within the jet-plate.

CAMM MODULE RETENTION FOR COMPRESSIVE MOUNT CONNECTOR AND HEATSINK
20260123425 · 2026-04-30 ·

An apparatus, comprising an interposer; a memory module, comprising a plurality of memory chips, and mounted to the interposer; and a heatsink, fastened to the interposer and configured to compress the interposer against the memory module.

Systems and methods for three channel galvanic isolator for inverter for electric vehicle
12620891 · 2026-05-05 · ·

A system includes: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: an upper phase multi-chip module including: a low-voltage upper phase controller; a high-voltage upper phase A controller; an upper phase A galvanic isolator connecting the low-voltage upper phase controller to the high-voltage upper phase A controller; a high-voltage upper phase B controller; an upper phase B galvanic isolator connecting the low-voltage upper phase controller to the high-voltage upper phase B controller; a high-voltage upper phase C controller; and an upper phase C galvanic isolator connecting the low-voltage upper phase controller to the high-voltage upper phase C controller.

Cooling cover and packaged semiconductor device including the same

Cooling covers including trapezoidal cooling chambers for cooling packaged semiconductor devices and methods of forming the same are disclosed. In an embodiment, a cooling cover for a semiconductor device includes an inlet; an outlet; and a cooling chamber in fluid communication with the inlet and the outlet, the cooling chamber having a trapezoidal shape in a cross-sectional view.

SEMICONDUCTOR MODULE
20260130219 · 2026-05-07 ·

In a semiconductor module, a resin housing is disposed on one surface of a cooler to provide a housing space together with the cooler. A substrate having a conductor is disposed in the housing space. A semiconductor element is joined to the conductor. A main terminal is inserted in the housing and joined to the conductor. A sealing body seals the substrate, the semiconductor element and a part of the main terminal in the housing space. A sealing material is interposed between the one surface of the cooler and a lower surface of the housing. A metal member having a fastening hole is integrated into the housing. The metal member protrudes from the lower surface of the housing and is in contact with the one surface of the cooler to provide a gap with a predetermined height between the lower surface and the one surface.