A semiconductor device includes first, second and third trenches formed in a semiconductor layer having a first conductivity type. Each trench includes a corresponding field plate and a corresponding gate over each field plate. A first body region having a second opposite conductivity type is between the first and second gates, and a second body region having the second conductivity type is located between the second and third gates. A first source region is located over the first body region and a second source region is located over the second body region, the first and second source regions having the first conductivity type. A first gate bus is conductively connected to the first gate and a second gate bus is conductively connected to the second gate, the first gate bus conductively isolated from the second gate bus.

An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.

This semiconductor device is provided with: a semiconductor layer; a cell that is provided on the semiconductor layer; an insulating film that covers the cell; a main electrode part that is superposed on the insulating film; a temperature-sensitive diode for sensing temperatures, the diode having a first electrode and a second electrode; and a connection electrode for diode, the connection electrode being used for the purpose of connecting the first electrode to the outside. The main electrode part has: a first bonding region to which a first conductive member is bonded; and a second bonding region to which a second conductive member is bonded. When viewed from the thickness direction of the semiconductor layer, the cell is provided on both a first semiconductor region in the semiconductor layer, and a second semiconductor region in the semiconductor layer.

A memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.

A semiconductor device includes: a semiconductor substrate in which an active region and a termination region are defined; a first gate pad arranged at the center of a first side of the active region; a first gate wiring connected to the first gate pad and extending in a first direction; first gate signal lines connected to the first gate pad or the first gate wiring and extending in a second direction; a second gate pad arranged at a corner of the first side of the active region; a second gate wiring connected to the second gate pad and having a portion extending in the first direction; and second gate signal lines connected to the second gate pad or the second gate wiring and extending in the second direction. The second gate wiring extends along a boundary between the active region and the termination region.

A semiconductor device includes: an active region having a semiconductor element and a surface electrode provided by a wiring electrode material and connected to the semiconductor element on a side adjacent to a surface of a semiconductor chip; and a pad arrangement region having a pad provided by the wiring electrode material. The pad arrangement region overlaps the active region in a direction normal to the surface of the semiconductor chip. In a part where the pad arrangement region and the active region overlap, the pad is disposed on the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure. In a part of the active region without overlapping the pad arrangement region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.