A manufacturing apparatus of a semiconductor device includes: a stage; a bonding head, including a mounting tool, a tool heater, and a lifting and lowering mechanism; and a controller performing bonding processing. The controller performs, in the bonding processing: first processing in which, after a chip is brought into contact with a substrate, as heating of the chip is started, the chip is pressurized against the substrate; distortion elimination processing in which, after the first processing and before melting of a bump, the lifting and lowering mechanism is driven in a lifting direction, thereby eliminating distortion of the bonding head; and second processing in which, after the distortion elimination processing, position control is performed on the lifting and lowering mechanism so as to cancel thermal expansion and contraction of the bonding head, thereby maintaining a gap amount at a specified target value.

A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

A packaging structure and a formation method thereof are provided. The packaging structure includes a carrier board, and a plurality of semiconductor chips adhered to the carrier board. Each semiconductor chip has a functional surface and a non-functional surface opposite to the functional surface, and a plurality of pads are formed on the functional surface of a semiconductor chip of the plurality of chips. A metal bump is formed on a surface of a pad of the plurality of pads, and a first encapsulation layer is formed on the functional surface. The packaging structure also includes a second encapsulation layer formed over the carrier board.

A radio frequency (RF) bridge that may include a body having an interfacing surface and a bonding surface extending from the interfacing surface. RF bridge may also include an interconnect operably engaged with the body. The interconnect may have at least one electrical connection positioned at the interfacing surface and at least another electrical connection positioned at the interfacing surface adjacent with the at least one electrical connection. The interconnect extends curvilinearly between the at least one electrical connection and the at least another electrical connection creating a curvilinear signal path.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.

The present disclosure relates to a method for manufacturing electronic chips comprising, in order:

a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed;

b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate;

c. forming first trenches of a first width on the side of a second face of the semiconductor substrate;

d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate;

e. forming second trenches of a second width, less than the first width, opposite the first trenches up to the metal contacts; and

f. forming third trenches opposite the second trenches, the third trenches extending through the metal contacts.

A method and an apparatus for forming an electronic device is provided. The method comprises: providing a substrate; disposing at least one electronic component on the substrate via a solder paste; applying microwave radiation to the substrate to reflow the solder paste; applying a vacuum pressure to the substrate to remove voids formed within the solder paste during the reflowing of the solder paste; solidifying the solder paste into solder bumps between the substrate and the at least one electronic component.

A package structure is provided. The package structure includes a dielectric structure and an antenna structure disposed in the dielectric structure. The package structure also includes a semiconductor device disposed on the dielectric structure and a protective layer surrounding the semiconductor device. The package structure further includes a conductive feature electrically connecting the semiconductor device and the antenna structure. A portion of the antenna structure is between the conductive feature and the dielectric structure.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.