A display module includes: a substrate having a mounting surface, four side surfaces, and a rear surface opposite to the mounting surface, the substrate including a thin film transistor layer (TFT) provided on the mounting surface; a plurality of inorganic light-emitting diodes provided on the mounting surface of the substrate; a side wiring electrically connected to the TFT layer and extending along a first pair of side surfaces among the four side surfaces of the substrate; a front cover covering the TFT layer and the plurality of inorganic light emitting devices in a first direction; a metal plate provided on the rear surface of the substrate; a side cover covering the side wiring and the four side surfaces; and a side member provided on a side of the side cover and grounded to the metal plate, wherein the side member is provided on a first side surface of the first pair of side surfaces along which the side wiring extends among the four side surfaces.

A semiconductor package may include a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip in a vertical direction, adhesive layers interposed between the first semiconductor chip and one of the second semiconductor chips and between the second semiconductor chips, and a molding member on the first semiconductor chip. Edges of the adhesive layers may be positioned inward from sidewalls of the second semiconductor chips. The molding member may cover at least sidewalls of the second semiconductor chips and sidewalls of the adhesive layers. The molding member may fill edge gaps defined by the sidewalls of the adhesive layers and edges of upper surfaces and lower surfaces of the second semiconductor chips.

A capacitor component includes a support member; capacitance laminates laminated on one surface of the support member; at least one insulating layer disposed between the capacitance laminates; and a plurality of through structures each penetrating through at least one of the capacitance laminates. Each of the capacitance laminates includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first and second electrode layers. One of the plurality of through structures includes a connection conductive pillar connected between first electrode layers of the capacitance laminates. Another of the plurality of through structures includes a first conductive pillar connected to a first electrode layer of one of the capacitance laminates, a dielectric through portion surrounding the first conductive pillar; and a through connection portion surrounding the dielectric through portion and connecting second electrode layers of the capacitance laminates to each other.

A hollow package includes a device substrate; a lid substrate provided above the device substrate; a first sealing ring provided on an upper surface of the device substrate; a second sealing ring provided on a lower surface of the lid substrate so as to face the first sealing ring; a seal layer that bonds the first sealing ring and the second sealing ring; and a functional element provided in a hollow portion surrounded by the device substrate, the lid substrate, the first sealing ring, the second sealing ring, and the seal layer, wherein the first sealing ring or the second sealing ring has a corner portion in a planar view, and the first sealing ring or the second sealing ring has a recess, which is recessed in a direction perpendicular to the upper surface of the device substrate, locally formed in a portion including the corner portion.

A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.

A display device includes electrodes spaced apart from each other in a display area, an insulating layer disposed on the electrodes, light emitting elements disposed between the electrodes on the insulating layer, a signal line electrically connected to the light emitting elements, and a pad electrode electrically connected to the signal line, the pad electrode and the electrodes being disposed on a same layer in a non-display area. The insulating layer includes an opening exposing the pad electrode, and the signal line does not overlap the opening of the insulating layer in plan view.

A method of fabricating integrated passive device dies includes forming a first plurality of integrated passive devices on a substrate, forming a plurality of micro-bumps on the first plurality of integrated passive devices such that the plurality of micro-bumps act as electrical connections to the integrated passive devices, and dicing the substrate to form an integrated passive device die including a second plurality of integrated passive devices. The micro-bumps may be formed in an array or staggered configuration and may have a pitch that is in a range from 20 microns to 100 microns. The integrated passive devices may each include a seal ring and the integrated passive device die may have an area that is a multiple of an integrated passive device area. The method may further include dicing the substrate in various ways to generate integrated passive device dies having different sizes and numbers of integrated passive devices.

A module and a substrate are provided in the present disclosure. The module includes an array substrate and a flexible circuit board. The array substrate includes a binding region including a first binding region and a second binding region; and in the binding region, the flexible circuit board is bound with the array substrate. In the first binding region, the array substrate includes a first conductive soldering pad; the flexible circuit board includes a second conductive soldering pad; and the first conductive soldering pad is electrically connected to the second conductive soldering pad. In the second binding region, the array substrate includes one or more of first soldering elements; the flexible circuit board includes one or more of second soldering elements; a first soldering element of the one or more of first soldering elements is fixed with a second soldering element of the one or more of second soldering elements.

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.