A semiconductor chip includes: a photonic integrated circuit (PIC) comprising an active component electrically connected to a first landing pad at a surface of the PIC, wherein the first landing pad is configured to receive a copper pillar, which, when installed, provides at least a portion of a first electrical interconnect between the active photonic component and a second integrated circuit to be stacked on the surface of the PIC, and wherein, when viewed from above the PIC towards the PIC, a center of the active photonic component on the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 m.

A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

The present disclosure provides a packaging device and a method to form the packaging device. The packaging device includes a package base, a die structure disposed over the package base, and a package lid over the die structure. The package lid is thermally coupled with the die structure and the package base.

A method includes: providing an active photonic component of a photonic integrated circuit (PIC); attaching two electrodes to the active photonic component of the PIC; providing a first landing pad on a front surface of the PIC, wherein, when viewed from a direction perpendicular to the front surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 m; and electrically connecting the first landing pad to one of the two electrodes.

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller under the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit disposed over and electrically connected to the memory controller, and a packaging substrate under and electrically connected to the memory controller. A die area of the memory controller is larger than the sum of a horizontal cross-section area of the memory stack and a die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV in each semiconductor die.

Methods and structures relating to bonding wafers using an aluminum nitride bonding layer with embedded metallization features. In some embodiments, the method may comprise forming a bonding layer on a first wafer where the bonding layer is formed of epitaxially grown aluminum nitride and where the first wafer is a silicon-based material and forming one or more metal features into the bonding layer on the first wafer. The first wafer may be hybrid bonded to a second wafer or die with one or more second metal features surrounded by a diffusion barrier layer. The one or more second metal features of the second wafer or die bonds to the one or more metal features of the first wafer. The diffusion barrier layer of the second wafer or die bonds, at least, to the bonding layer of the first wafer.

Methods and structures relating to bonding wafers using an aluminum nitride bonding layer. In some embodiments, the method may comprise forming a bonding layer of aluminum nitride on a first wafer where the aluminum nitride is grown epitaxially onto the first wafer and bonding the first wafer to a second wafer or die using a low temperature bonding process of less than 400 degrees Celsius. The aluminum nitride may be epitaxially grown using a physical vapor deposition (PVD) process, a metal organic chemical vapor deposition (MOCVD) process, or a molecular-beam epitaxy (MBE) process. The carrier wafer may be silicon with a (111) crystal structure orientation or 4H-silicon carbide with a (001) crystal structure orientation at the interface with the bonding layer.

An example of a semiconductor package includes a buffer die having a first planarize area, a memory die stack structure including middle core dies and a top core die stacked on the buffer die in a vertical direction and having a second planar area smaller than the first planar area, an adhesion layer contacting an upper surface of the memory die stack structure, a dummy die contacting the adhesion layer and having a third planar area greater than the first planar area, and a molding structure under the dummy die and covering sidewalls of the buffer die, the memory die stack structure and the adhesion layer.

A heat sink, a thermal module, and an electronic device are provided. The heat sink includes a base and a plurality of curved fins arranged in parallel on the base. Each curved fin has a plurality of wave peaks, with a pitch defined between any two adjacent wave peaks, and at least two of the plurality of wave peaks are different.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.