A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.

A semiconductor structure may be provided by forming a first molding compound around a first semiconductor die such that a top surface of the first molding compound is coplanar with a top dielectric surface of the first semiconductor die; forming a combination of at least one bonding-level dielectric layer, first bonding pads, and dummy pads over the first semiconductor die and the first molding compound, wherein each of the bonding pads is formed directly on a respective conductive structure within the first semiconductor die; and attaching a second semiconductor die including second bonding pads therein to the first semiconductor die by performing a bonding process that bonds the second bonding pads to the first bonding pads by metal-to-metal bonding such that a first subset of the dummy pads has an areal overlap in a plan view with the second semiconductor die.

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

The semiconductor package includes a semiconductor chip; a first bonding layer including a first inner bonding layer and a first outer bonding layer sequentially stacked on the semiconductor chip along a vertical direction; first inner bonding pads accommodated in the first inner bonding layer on the bonding region of the substrate, and first inner align key patterns accommodated in the first inner bonding layer on the align key region of the substrate; first outer bonding pads accommodated in the first outer bonding layer on the bonding region of the substrate and first outer align key patterns accommodated in the first outer bonding layer on the bonding region of the substrate; a second bonding layer including a second outer bonding layer and a second inner bonding layer sequentially stacked on the first bonding layer along the vertical direction; and a second semiconductor chip disposed on the second bonding layer.

Provided is a multi-dies stacking structure, which includes: a plurality of core dies stacked, wherein each core die comprises a first sub-core die and a second sub-core die vertically stacked; adjacent core dies are interconnected through micro-metal bumps, and the first sub-core die is interconnected with the second sub-core die through hybrid bonding members.