A semiconductor package may include a substrate including a connection circuit, a redistribution structure, and a chip structure on the redistribution structure. The redistribution structure may include a rear redistribution layer electrically connected to the connection circuit, a first semiconductor chip between rear and front redistribution portions and electrically connection to a front redistribution layer of the front redistribution portion, a first molded portion covering at least a portion of the first semiconductor chip, and a first through-via passing through the first molded portion and electrically connecting the front and the rear redistribution layers. The chip structure may include a wiring portion having a wiring layer electrically connected to the front redistribution layer, second and third semiconductor chips on the wiring portion and electrically connected to the wiring layer, and a second molded portion covering at least a portion of each of the second and third semiconductor chips.

An electronic package and a manufacturing method thereof are provided. A semiconductor component and an optoelectronic component are provided on a carrier structure. The optoelectronic component is covered with a shielding layer, and an encapsulation layer is formed to cover the semiconductor component and the optoelectronic component. The shielding layer is removed to expose the optoelectronic component, allowing subsequent connection of an optical device on the optoelectronic component. The process of the Co-packaged optics module is simplified.

A semiconductor package assembly is provided. The semiconductor package assembly includes a substrate, an interposer, a first die, a second die, and a dummy die structure. The interposer is disposed on the substrate. The interposer includes a central region and a peripheral region. The peripheral region includes a corner region and a non-corner region. The first die is disposed on the interposer in the central region. The second die is disposed beside the first die and is located in the non-corner region of the peripheral region of the interposer. The dummy die structure is disposed beside the first die and the second die and is located in the corner region of the peripheral region of the interposer. The dummy die structure includes dummy dies stacked on each other in a first direction.

A semiconductor package may include a first semiconductor die having a first width; a second semiconductor die on the first semiconductor die, the second semiconductor die having a second width that is smaller than the first width; and a mold layer at least partially covering a side surface of the second semiconductor die, and a top surface of the first semiconductor die, wherein the first semiconductor die comprises at least one first detection pattern, the at least one first detection pattern being on the top surface of the first semiconductor die and in contact with a bottom surface of the mold layer.

Embodiments of the present disclosure provide a semiconductor package. The semiconductor package includes: a first semiconductor chip, a second semiconductor chip, and a first material layer arranged between the first semiconductor chip and the second semiconductor chip, where the first material layer includes a non-conductive substrate as well as a first-type filler and a second-type filler that are distributed in the non-conductive substrate, and the average particle size of the first-type filler is different from the average particle size of the second-type filler. In the embodiments of the present disclosure, two types of fillers with different particle sizes are utilized in combination to increase the filling ratio of the fillers and improve the CTE of the material layers.

A semiconductor package may include at least one semiconductor chip including a lower surface, an upper surface and connection pads, the lower surface facing the substrate, the upper surface opposite to the lower surface, the connection pads being on the upper surface; bonding wires electrically connecting the connection pads to the interconnection; an adhesive film having a first surface, a second surface, and fillers, the first surface in contact with the lower surface of the at least one semiconductor chip, the second surface opposite to the first surface, the fillers oriented in a vertical direction between the first surface and the second surface; and connection bumps below the substrate and electrically connected to the interconnection, wherein the adhesive film has stripe patterns defined by the fillers and extend from the first surface to the second surface, and the stripe patterns are spaced apart from each other in a horizontal direction.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. The redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. The alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.

Various embodiments of the present technology may provide a method for fabricating a semiconductor structure. The method may include receiving a source substrate having a dielectric layer and a conductive feature, selectively depositing a barrier layer only on a top surface of the conductive feature, modifying a top surface of the dielectric layer, and removing the barrier layer after modifying the dielectric layer. The method may also include cleaning a top layer of the dielectric and conductive feature prior to depositing the barrier layer.

Provided is a semiconductor package including a package substrate, a first semiconductor device arranged on the package substrate, a second semiconductor device arranged on the first semiconductor device, a heat dissipation structure arranged on the second semiconductor device, and at least one first chip stack including a plurality of first core chips apart from the first semiconductor device in a lateral direction and sequentially stacked on the package substrate and a first buffer chip arranged on the second semiconductor device and the plurality of first core chips, wherein the heat dissipation structure is arranged apart from the first buffer chip in the lateral direction, and the plurality of first core chips include a plurality of first core through electrodes configured to penetrate at least a portion of each of the plurality of first core chips.

A semiconductor device has a substrate formed on a first carrier. A semiconductor die is mounted on the substrate. An interconnect structure is formed on a second carrier. A copper pillar is formed on the substrate or interconnect structure. The interconnect structure is disposed over the substrate with the copper pillar and semiconductor die between the substrate and interconnect structure. The first carrier and second carrier are removed after disposing the interconnect structure over the substrate. A system-in-package (SiP) is mounted to the substrate opposite the semiconductor die after removing the first carrier.