Patent classifications
H10W74/131
REDUCED WARPAGE ELECTRONIC PACKAGE AND PACKAGING STRUCTURE
An electronic package is provided which includes a continuous stiffener element (i.e., frame) located around a semiconductor die. The continuous stiffener element has a coefficient of thermal expansion (CTE) that closely matches the CTE of a carrier substrate that is located beneath the semiconductor die. The closely matched CTA between the continuous stiffener element and the carrier substrate reduced warpage in an electronic package containing the same. A molding component can be disposed between the continuous stiffener element and the semiconductor die. The electronic package having the reduced warpage can be used as a component of an electronic packaging structure.
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.