A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

A semiconductor device includes a wiring layer, a dielectric layer covering the wiring layer, a thin film resistor provided on the dielectric layer, and a plug electrode connecting the thin film resistor to the wiring layer. The plug electrode includes a barrier layer and a buried layer. The buried layer is configured by the filling portion filling a region surrounded by a first incline surface, and an extension portion extending from the filling portion along a second incline surface. The thin film resistor is in contact with the filling portion and the extension portion of the plug electrode. A second incline angle between the second incline surface and a main surface of a semiconductor substrate is smaller than a first incline angle between the first incline surface and the main surface of the semiconductor substrate.

A semiconductor device includes: an active region having a semiconductor element and a surface electrode provided by a wiring electrode material and connected to the semiconductor element on a side adjacent to a surface of a semiconductor chip; and a pad arrangement region having a pad provided by the wiring electrode material. The pad arrangement region overlaps the active region in a direction normal to the surface of the semiconductor chip. In a part where the pad arrangement region and the active region overlap, the pad is disposed on the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure. In a part of the active region without overlapping the pad arrangement region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.

A circuit structure and a method of manufacturing a circuit structure are provided. The circuit structure includes a first metal line and a second metal line. The second metal line is disposed over the first metal line. At least one air gap is disposed between the first metal line and the second metal line.

A semiconductor device having a semiconductor substrate with first and second main surfaces that face one another in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer has a first electrode layer on the semiconductor substrate, a dielectric layer on the first electrode layer, a second electrode layer on the dielectric layer, and first and second outer electrodes electrically connected to the first and second electrode layers, respectively. The semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate and on the side of the first end surface. In the first end-portion region, a first exposed portion is provided that is exposed between the first main surface and the first end surface.

A method includes forming a transistor over a substrate; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure comprises a high resistance (HiR) resistor, and the HiR resistor is made of titanium nitride (TiN) or tantalum nitride (TaN); bonding a carrier substrate to the front-side interconnect structure through a metal-containing material; and forming a backside interconnect structure over a backside of the substrate.

A semiconductor device includes a substrate, first, second, and third fins protruding from the substrate, first, second and third source/drain (S/D) features over the first, second, and third fins, respectively, a first isolation feature over the substrate and disposed between the first and second S/D features, a second isolation feature over the substrate and disposed between the second and third S/D features, and a dielectric layer disposed on sidewalls of the first, second, and third S/D features and on sidewalls of the first and second isolation features. A top surface of the first isolation feature is above a top surface of the second isolation feature.

A semiconductor device includes a substrate, first, second, and third fins protruding from the substrate, first, second and third source/drain (S/D) features over the first, second, and third fins, respectively, a first isolation feature over the substrate and disposed between the first and second S/D features, a second isolation feature over the substrate and disposed between the second and third S/D features, and a dielectric layer disposed on sidewalls of the first, second, and third S/D features and on sidewalls of the first and second isolation features. A top surface of the first isolation feature is above a top surface of the second isolation feature.

A semiconductor module includes: a first semiconductor chip and a second semiconductor chip, each formed with a switching element; a first heat sink disposed adjacent to a second surface of the semiconductor module with respect to the first semiconductor chip, and on which the first semiconductor chip is mounted; a second heat sink disposed adjacent to the second surface with respect to the second semiconductor chip, and on which the second semiconductor chip is mounted; an encapsulating member encapsulating the first and second semiconductor chips; a first heat dissipation wiring layer disposed adjacent to a first surface of the semiconductor module with respect to the first semiconductor chip and thermally connected to the first semiconductor chip; and a second heat dissipation wiring layer disposed adjacent to the first surface with respect to the second semiconductor chip and thermally connected to the second semiconductor chip.