A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in a first region, and the first source/drain epitaxial feature is asymmetric with respect to a fin. The structure further includes a second source/drain epitaxial feature disposed in the first region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, and a conductive feature disposed over the first and second source/drain epitaxial features and the first dielectric feature.

A modular POL component can be arranged to define a half-bridge converter topology, and can be coupled with other modular POL power components to define a full-bridge or 3-phase AC converter topology based on a desired power output. The assembled POL components can be mounted on a common electrically insulative substrate to define a POL power conversion device to provide the desired power output.

An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.

A semiconductor storage device including a two-port SRAM cell, in which nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.

Methods of forming an integrated circuit devices may include providing first and second active regions, an isolation layer, and first and second sacrificial stack structures. The first and second sacrificial stack structures may contact the first and second active regions, and the first and second sacrificial stack structures may each include a channel layer and a sacrificial layer. The methods may also include forming an etch stop layer on the isolation layer, replacing portions of the first and second sacrificial stack structures with first and second source/drain regions, forming a front contact including a front contact plug, forming a back-side insulator, and forming a back contact plug in the isolation layer and the back-side insulator. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.

Techniques are provided herein to form semiconductor devices within a standard unit cell having topside metal tracks that are offset from backside metal tracks. Stacked transistors are provided such that a source or drain region of one device is located vertically over the source or drain region of the other device. Both frontside and backside contacts may be formed to contact either top or bottom surfaces of the corresponding source or drain regions. Topside metal tracks are used to provide signal and power to various transistor elements of the top semiconductor device while backside metal tracks are used to provide signal and power to various transistor elements of the bottom semiconductor device. The topside tracks are offset from the backside tracks such that one topside track is aligned along one boundary of a standard unit cell and one backside track is aligned along the opposite standard unit cell boundary.

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.

An integrated circuit includes (i) a first transistor device having a first source or drain region coupled to a first source or drain contact, and a first gate electrode, (ii) a second transistor device having a second source or drain region coupled to a second source or drain contact, and a second gate electrode, (iii) a first dielectric material above the first and second source or drain contacts, (iv) a second dielectric material above the first and second gate electrodes, (v) a third dielectric material above the first and second dielectric materials, and (vi) an interconnect feature above and conductively coupled to the first source or drain contact. In an example, the interconnect feature comprises an upper body of conductive material extending within the third dielectric material, and a lower body of conductive material extending within the first dielectric material, with an interface between the upper and lower bodies.