A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion connecting the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, and a dummy via through the second dielectric layer and directly contacting the terminal portion. In a cross-sectional view, a width of the dummy via is smaller than 50% of a width of the conductive via.

A capacitive isolator is developed. Embodiments of the capacitive isolator include a substrate; a shallow trench isolation region coupled to the substrate; a polysilicon layer disposed above the shallow trench isolation region; a bottom metal plate disposed above the polysilicon layer; one or more lower dielectric layers above the bottom metal plate; an intermediate metal plate disposed above the one or more lower dielectric layers; and a top metal plate disposed above the intermediate metal plate. A semiconductor device including two capacitive isolators and an isolation structure disposed between the two capacitive isolators is also developed.

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

Various implementations of backside and topside routing of bitlines and wordlines in memory arrays are disclosed. Bitlines in backside and topside metal layers may be alternated between adjacent bit cells in a memory array. Alternating the location of the bitlines between bit cells in the memory array may reduce bitline capacitance in a memory array. Placing wordlines in backside metal layers may allow dual wordlines to be implemented across a span of bit cells in a memory array. The dual wordlines may be alternately connected to adjacent bit cells, thereby allowing selective toggling of bit cells based on the wordline transmitting a control signal.

A method of forming a semiconductor device includes the following operations. A substrate is provided with an electric component. A composite dielectric layer is formed on the substrate and covers the electric component. An opening is formed through the composite dielectric layer. A directional etching process is performed to widen an upper portion of the opening. A metal feature is formed in the opening.

A circuit structure and a method of manufacturing a circuit structure are provided. The circuit structure includes a first metal line and a second metal line. The second metal line is disposed over the first metal line. At least one air gap is disposed between the first metal line and the second metal line.

An electronic device is provided. The electronic device includes a substrate, a first conductive pad and a floating pad. The first conductive pad is disposed on the substrate. The floating pad is disposed on the substrate and adjacent to the first conductive pad. The floating pad includes a metal frame, and an inner edge of the metal frame defines an outline of an observation region. In addition, in a bottom-view diagram of the electronic device, the outline of the observation region has at least one arc-shaped edge.

A storage device includes a substrate of a memory package and a first memory die. The substrate includes a controller and a first pin pad, the first pin pad being electrically connected to the controller and defining a data channel for data communications. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a redistribution layer electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.

A semiconductor device includes a lead, a semiconductor substrate, a back-surface electrode provided between the semiconductor substrate and the lead, and a solder layer configured to connect the back-surface electrode and the lead. The back-surface electrode includes a silicide layer formed on a back surface of the semiconductor substrate, a bonding layer formed on the lead, a barrier layer formed on the bonding layer, and a stress relaxation layer formed between the silicide layer and the barrier layer. The stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component.

An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.