A package comprising a first integrated device; a second integrated device coupled to the first integrated device through an adhesive; a first plurality of wire bonds coupled to the first integrated device; a second plurality of wire bonds coupled to the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, the first plurality of wire bonds and the second plurality of wire bonds; and a plurality of pillar interconnects.

A semiconductor package includes a substrate, a first semiconductor die disposed on the substrate, a second semiconductor die stacked on the first die and offset from it in a first direction and a second direction that are perpendicular to each other, and a third semiconductor die stacked on the first and second dies and offset from them in the first direction. The first semiconductor die includes a first pad and a second pad, arranged successively in the second direction. The second semiconductor die includes a third pad and a fourth pad, and the third semiconductor die includes a fifth pad and a sixth pad, each arranged successively in the second direction. A first conductive pattern connects the first and fifth pads, while a second conductive pattern connects the second, fourth, and sixth pads. The first and second conductive patterns are spaced apart from the third pad.

An embodiment provides a semiconductor package including a package substrate including substrate pads, and a chip stack including a plurality of semiconductor chips stacked on the package substrate, wherein the plurality of semiconductor chips include first and second semiconductor chips having the same size and shape device region, the first and second semiconductor chips include first and second chip pad regions protruding from different regions of a first side of the device region, respectively, and each chip pad being connected to a substrate pad by a wire, and the first and second semiconductor chips are stacked such that the first and second chip pad regions face in the same horizontal direction and do not overlap each other in a stacking direction.

An electronic package is provided, in which an electronic element is arranged on a carrier structure having a plurality of wire-bonding pads arranged on a surface of the carrier structure, and a plurality of bonding wires are connected to a plurality of electrode pads of the electronic element and the plurality of wire-bonding pads. Further, among any three adjacent ones of the plurality of wire-bonding pads, a long-distanced first wire-bonding pad, a middle-distanced second wire-bonding pad and a short-distanced third wire-bonding pad are defined according to their distances from the electronic element. Therefore, even if the bonding wires on the first to third wire-bonding pads are impacted by an adhesive where a wire sweep phenomenon occurred when the flowing adhesive of a packaging layer covers the electronic element and the bonding wires, the bonding wires still would not contact each other, thereby avoiding short circuit problems.

A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).

A power module is provided. The power module includes a substrate, a chip mounted on the substrate and having a signal pad, and a lead portion electrically connected to the chip. The lead portion includes a signal lead provided to be spaced apart from the substrate, and a connecting lead connecting the signal lead and the signal pad.

A semiconductor device, a semiconductor package including such a semiconductor device and a method of manufacturing such a semiconductor package are presented. The semiconductor device includes a die and a leadframe. The semiconductor device further includes a wire-bond interconnect structure including one or more pairs of wires. Herein, a pair of wires includes two wires that are bonded together at one end at the die and that are bonded together on the other end at the leadframe.