One or more dielectric inserts are formed in a through-substrate interconnect structure to prevent, minimize, and/or otherwise reduce the amount of dishing that occurs in the top surface of the through-substrate interconnect structure during planarization of the through-substrate interconnect structure. The dielectric insert(s) are formed of a dielectric material having a hardness that is greater than the hardness of the metal material of the through-substrate interconnect structure. The greater hardness enables the dielectric insert(s) to resist material removal during planarization of the through-substrate interconnect structure, which enables a high uniformity in the material removal rates across the top surface of the through-substrate interconnect structure to be achieved. The reduced amount of dishing during planarization of the through-substrate interconnect structure reduces the likelihood of removal of liner material from one or more liners between the sidewalls of the through-substrate interconnect structure and the substrate layer.

Some embodiments relate to an integrated chip having a memory cell over a substrate. The memory cell includes a first electrode. An electrode contact is on an upper surface of the first electrode. A width of an upper surface of the electrode contact is greater than a width of the upper surface of the first electrode and a thickness of the electrode contact. A first conductive interconnect structure contacts the upper surface of the electrode contact. A width of the first conductive interconnect structure is greater than the width of the upper surface of the electrode contact. A second conductive interconnect structure overlies the first conductive interconnect structure. Thicknesses of the first and second conductive interconnect structures are greater than the thickness of the electrode contact.