According to one embodiment, a semiconductor device includes a semiconductor chip, a first conductor which includes a first portion exposed from a first surface of a sealing resin facing to a first direction, a second portion projecting from a second surface of the sealing resin facing to a second direction, and a bent portion connecting the first portion and the second portion, a second conductor exposed from a third surface of the sealing resin opposed to the first surface and having a thickness in the first direction which is greater than a thickness of the first conductor, a third conductor provided between the semiconductor chip and the first conductor, a first bonding material which bonds the semiconductor chip and the second conductor, a second bonding material which bonds the semiconductor chip and the third conductor, and a third bonding material which bonds the third conductor and the first conductor.

A described example includes a method for fabricating an integrated circuit (IC) device. The method can include forming a mask on a surface of a multi-layer substrate, in which the multi-layer substrate includes at least one leadframe having spaced apart regions of copper distributed across and extending from the surface into at least one layer of the multi-layer substrate. The method can also include forming nanotwin copper bond pads on the surface of the multi-layer substrate over a respective region of the regions of copper. The method can also include removing the mask and forming a layer of an insulating material over the surface of the multi-layer substrate and around the nanotwin copper bond pad.

In a described example, an apparatus includes: a package substrate with conductive leads; a semiconductor die mounted to the package substrate, the semiconductor die having a first thickness; electrical connections coupling bond pads on the semiconductor die to conductive leads on the package substrate; brackets attached to the package substrate spaced from the semiconductor die and extending away from the package substrate to a distance from the package substrate that is greater than the first thickness of the semiconductor die; and mold compound covering the package substrate, the semiconductor die, the brackets, and the semiconductor die to form a semiconductor device package having a board side surface and a top surface opposite the board side surface, and having portions of the brackets exposed from the mold compound on the top surface of the semiconductor device package to form mounts for a passive component.

A package includes a first direct bonded metal (DBM) substrate, a first semiconductor die disposed on a top surface of the first DBM substrate, a second DBM substrate disposed at a height above the first DBM substrate, and a second semiconductor die disposed on a top surface of the second DBM substrate. A wire bond is made between the first semiconductor die disposed on the top surface of the first DBM substrate and the second semiconductor die disposed on the top surface of the second DBM substrate.

The present disclosure proposes a semiconductor device, as well as a method for manufacturing such a semiconductor device, and related to a method of generating a dual exposed drain with common gate and source clip-bonded package for reverse battery protection. The semiconductor device includes a first lead frame with an external first lead frame terminal and a first die paddle, a second lead frame with an external second lead frame terminal and a second die paddle, a common clip with an external source clip terminal, a two source contacts, a common gate clip with an external common clip gate terminal, a clip contact and a gate clip contact, a first semiconductor die with a first die gate terminal, a first die source terminal, and a first die drain terminal, a second semiconductor die with a second die gate terminal, a second die source terminal, and a second die drain terminal.

An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

A semiconductor device has a substrate. An electrical component is disposed over a first surface of the substrate. A solder paste is disposed over the first surface of the substrate. A conductive pillar is disposed on the solder paste. An encapsulant is deposited over the first surface of the substrate, the electrical component, and the conductive pillar. A solder bump is formed over the conductive pillar.

A package includes a first leadframe including a plurality of leads and a conductor, a first semiconductor die mounted on a first surface of the first leadframe and attached to a first subset of the plurality of leads and the conductor, and a second semiconductor die mounted on the first surface of the first leadframe and attached a second subset of the plurality of leads and the conductor. The conductor provides a direct electrical connection for an electrical signal between the first semiconductor die and the second semiconductor die. The package further includes a second leadframe. The first leadframe is mounted on the second leadframe via a second surface of the first leadframe, the second surface opposite the first surface. The second leadframe provides a ground return path between the between the first semiconductor die and the second semiconductor die for the electrical signal.