H10W70/427

Semiconductor wireless transmitter/receiver with chip carrier having integrally formed antenna

A semiconductor device comprises a semiconductor chip and an electrically conductive chip carrier, wherein the semiconductor chip is mounted on the chip carrier. The semiconductor device furthermore comprises an electrically conductive extension element mechanically connected to the chip carrier, wherein the extension element and the chip carrier are formed as an integral single piece. A part of the chip carrier which has the extension element is configured as an antenna.

Molded module package with an EMI shielding barrier

An electronic device that includes a substrate and a die disposed on the substrate, the die having an active surface. Wire bonds are attached from the active surface of the die to the substrate. A radiation barrier is attached to the substrate and disposed over the die. The radiation barrier is configured to mitigate electromagnetic radiation exposure to the die. A mold compound is formed over the die, the wire bonds, and the radiation barrier.

DELAMINATION MITIGATION FOR AN INTEGRATED CIRCUIT

An electronic device includes a leadframe, where the leadframe includes inner leads, external leads, and die attach portions. The leadframe has channels defined at a junction between the die attach portions and the inner leads, where the channel mitigates crack propagation along a path of the die attach portions. A die assembly is attached to the die attach portions and copper pillars are provided to connect the die assembly to the die attach portions. A mold compound encapsulates the die assembly, the inner leads, the die attach portions, and the copper pillars.

PACKAGE MANUFACTURABLE USING THERMOPLASTIC STRUCTURE COVERING A COMPONENT ASSEMBLY SECTION WITHOUT COVERING A LEAD SECTION
20260040955 · 2026-02-05 · ·

A package and method is disclosed. In one example, the package comprises a component assembly section, at least one electronic component being assembled with the component assembly section, at least one lead section being electrically coupled with the at least one electronic component and/or with the component assembly section, an encapsulant at least partially encapsulating the at least one electronic component and partially encapsulating the component assembly section and the at least one lead section so that part of the component assembly section and part of the at least one lead section are exposed beyond the encapsulant. A thermoplastic structure covers an exposed area of the component assembly section without covering an exposed area of the at least one lead section.

SEMICONDUCTOR PACKAGE INCLUDING A MOLDED INTERCONNECT
20260040964 · 2026-02-05 ·

A semiconductor package contains a first semiconductor die, electrically coupled to a plurality of leads around a perimeter of the semiconductor package via a molded interconnect. The molded interconnect comprises a plurality of embedded interconnects in a first mold compound which electrically couple the plurality of bond pads of the first semiconductor die to the plurality of leads of the semiconductor package. The molded interconnect may have a greater cross-sectional area at a given pitch compared to a similar wire bonded semiconductor package and allow advantageous thermal management of the semiconductor package compared to other electrical coupling techniques. The molded interconnect may allow small high-power integrated circuits to be packaged with a package footprint which is smaller than would otherwise be available.

Universal Surface-Mount Semiconductor Package

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

Small outline TVS package compromising lead clip coin structure to support a semiconductor device

A discrete semiconductor package includes a semiconductor device, a left lead, and a right lead. The semiconductor device has a first side and a second side, the second side being opposite the first side. The left lead has a left terminal and a platform to support the semiconductor device on the first side. The right lead has a right terminal and a clip coin to support the semiconductor device on the second side.

Semiconductor device

A semiconductor device includes a laminate including a semiconductor element, an insulating substrate on a first surface of the semiconductor element, an interconnect on the insulating substrate, and an interconnect member on a second surface of the semiconductor element. The interconnect is electrically connected to a first electrode in the first surface of the semiconductor element through a through hole in the insulating substrate. The interconnect member is electrically connected to a second electrode in the second surface of the semiconductor element. The semiconductor device further includes first and second elastic terminals holding the laminate therebetween. The first terminal includes a bulge that engages with a depression in the interconnect. The second terminal contacts the interconnect member. The semiconductor device further includes a fixing member fixing the first terminal and the second terminal while electrically isolating the first terminal and the second terminal from each other.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
20260082988 · 2026-03-19 · ·

A semiconductor device includes: a heat dissipation base; a case including an outer peripheral wall that has an inner surface facing an inside of the case and a wiring terminal provided integrally with the outer peripheral wall, the wiring terminal having an inner end portion, which is on one end of the wiring terminal and is exposed to the inside of the case from the inner surface of the outer peripheral wall; a sealing member sealing the inside of the case; and an adhesion member embedded in the inner surface of the case and having an adhesion surface exposed from the inner surface, the adhesion member and the heat dissipation base being on different sides of the inner end portion. The adhesion surface has higher adhesion to the sealing member than the outer peripheral wall.

PACKAGE GROOVES TO INHIBIT DELAMINATION
20260096450 · 2026-04-02 ·

A semiconductor package includes a semiconductor die; a die pad having a first surface coupled to the semiconductor die and a second surface opposite the first surface, the die pad including an extension that comprises a first V-shaped groove in the second surface; a first conductive terminal having first and second ends and a third surface facing a same direction as the second surface, the third surface comprising a second V-shaped groove; a second conductive terminal having third and fourth ends and a fourth surface facing the same direction as the second surface, the fourth surface comprising a third V-shaped groove, the extension in between the second and fourth ends; and a mold compound covering the die, the die pad, and the first and second conductive terminals, the mold compound filling the first, second, and third V-shaped grooves, and the first and third ends extending to an exterior of the mold compound.