A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Methods and structure for gate-all-around (GAA) semiconductor device that can support multiple threshold voltages. The semiconductor device can include a first channel. The first channel can overlaid by a first dielectric layer. The first dielectric layer can be overlaid by a second dielectric layer. The semiconductor device can include a second channel. The second channel can be overlaid by a third dielectric layer. The first dielectric layer can be a doped dielectric layer. The the third dielectric layer can be overlaid by a fourth dielectric layer. The semiconductor device can include a work-function metal layer overlaying the second dielectric layer and the fourth dielectric layer. The work-function metal layer can have a uniform thickness

This disclosure is directed to a method of improving a quality of an interfacial layer of a gate structure of a semiconductor device. The method includes forming a channel region on a substrate and oxidizing a surface of the channel region to form the interfacial layer including silicon oxide. The method further includes depositing a layer of metal oxide (e.g., yttrium oxide) on the interfacial layer, performing an annealing process to transform silicon oxide in the interfacial layer into silicon dioxide by reducing a density of oxygen vacancies in the interfacial layer, and removing the layer of metal oxide. The method further includes forming a high-k dielectric layer and a gate electrode on the interfacial layer to form the gate structure.