A semiconductor structure including an active region and an isolation region adjacent to the active region and a gate arranged over the active region and the isolation region is provided. A first gate contact and a second gate contact is arranged over the gate. The first gate contact overlaps the active region and the second gate contact overlaps the isolation region. A metal line extends over the first gate contact and the second gate contact.

A method for manufacturing a semiconductor device is provided. The method includes forming an epitaxial stack over a substrate, the epitaxial stack comprising at least one first semiconductor layer, at least one first sacrificial layer, at least one second semiconductor layer, and at least one second sacrificial layer; replacing the dummy gate structure, the at least one first sacrificial layer, and the at least one second sacrificial layer with a high-k/metal gate structure; and performing a planarization process on the high-k/metal gate structure, such that a first portion of the high-k/metal gate structure over the at least one second semiconductor layer has a height less than a height of a second portion of the high-k/metal gate structure between the at least one first semiconductor layer and the at least one second semiconductor layer.

An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.