A semiconductor device includes a substrate having a first surface, a second surface, and an opening; a semiconductor device layer having a third surface and a fourth surface; a heat transfer member; source electrodes disposed on a fourth surface; and electrically conductive vias that penetrate the semiconductor device layer and a diamond layer to electrically connect the source electrodes to a metal layer. The heat transfer member includes the diamond layer and the metal layer, the diamond layer covers a bottom surface and an inner wall surface of the opening, and the metal layer is disposed on the diamond layer.

A power module includes a first end power semiconductor element and a second end power semiconductor element. A first sum is a sum of a path length between the gate electrode of the first end power semiconductor element and a first control terminal and a path length between the source electrode of the first end power semiconductor element and a first detection terminal. A second sum is a sum of a path length between the gate electrode of the second end power semiconductor element and the first control terminal and a path length between the source electrode of the second end power semiconductor element and the first detection terminal. The power module includes a first control layer connected to the gate electrode. The first control layer includes a first detour portion that detours the path to reduce a difference between the first sum and the second sum.

A switching module includes at least one substrate, at least one switching element, at least one control loop, a first power part and a second power part. The at least one switching element is disposed on the at least one substrate. The at least one control loop is connected with the corresponding switching element. The first power part is connected with the corresponding switching element. The second power part is connected with the corresponding switching element. A direction of a first current flowing through the first power part and a direction of a second current flowing through the second power part are identical. A projection of the first power part on a reference plane and a projection of the second power part on the reference plane are located at two opposite sides of a projection of the control loop on the reference plane.

An electronic circuit module. The module has a multilayered LTCC circuit carrier made of structured inorganic substrate layers, which have electrical and/or thermal conduction structures for electrical and/or thermal conduction, at least one electronic component, which is arranged on a first side and/or an opposite second side of the LTCC circuit carrier, and at least one SiC power semiconductor. The at least one SiC power semiconductor is embedded in the multilayered LTCC circuit carrier and enclosed at least on three sides by the multilayered LTCC circuit carrier. Connection contacts of the SiC power semiconductor contact the electrical and/or thermal conduction structures of the LTCC circuit carrier.

A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

A semiconductor device includes: a plurality of semiconductor elements connected in parallel; a rectifier element connected in anti-parallel to the plurality of semiconductor elements; a power terminal electrically connected to the plurality of semiconductor elements; and an electrical conductor electrically connected to the power terminal and the plurality of semiconductor elements and including a pad portion to which the plurality of semiconductor elements are bonded. The plurality of first semiconductor elements include a first element and a second element. The minimum conduction path of the first element to the power terminal is shorter than the minimum conduction path of the second element to the power terminal. The pad portion includes a first section to which the first element is bonded and a second section to which the second element is bonded. The rectifier element is located in the first section of the pad portion.

A display module is disclosed. The display module includes a substrate; a plurality of inorganic light-emitting diodes provided in a plurality of mounting grooves formed in the substrate, the plurality of inorganic light-emitting diodes including an inorganic light-emitting diode that has a first chip electrode and a second chip electrode; a first substrate electrode pad and a second substrate electrode pad provided at a bottom surface of a mounting groove from among the plurality of mounting grooves, the first substrate electrode pad being electrically coupled to the first chip electrode and the second substrate electrode pad being electrically coupled to the second chip electrode; and a third substrate electrode pad and a fourth substrate electrode pad provided around the mounting groove.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

A semiconductor device includes a semiconductor chip having first and second main electrodes disposed on opposite surfaces of a silicon carbide substrate, first and second heat dissipation members disposed so as to sandwich the semiconductor chip, and joining members disposed between the first main electrode and the first heat dissipation member and between the second main electrode and the second heat dissipation member. At least one of the joining members is made of a lead-free solder having an alloy composition that contains 3.2 to 3.8 mass % Ag, 0.6 to 0.8 mass % Cu, 0.01 to 0.2 mass % Ni, x mass % Sb, y mass % Bi, 0.001 to 0.3 mass % Co, 0.001 to 0.2 mass % P, and a balance of Sn, where x and y satisfy relational expressions of x+2y11 mass %, x+14y42 mass %, and x5.1 mass %.

A light emitting device includes a short wavelength light emitting portion, a long wavelength light emitting portion, and a coupling layer combining the short wavelength emitting portion and the long wavelength light emitting portion. Each of the short wavelength light emitting portion and the long wavelength light emitting portion includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. The active layer of the long wavelength light emitting portion contains more Indium (In) than the active layer of the short wavelength light emitting portion, and the short wavelength light emitting portion emits light of a shorter wavelength than that of light emitted from the long wavelength light emitting portion.