An electronic device package includes a frame, an electronic device mounted to the frame, surface-mount leads, and a gel at least partially filling a cavity between the electronic device and the frame. The electronic device includes electronic circuitry provided on an electronic device substrate, and the surface-mount leads are electrically connected to the electronic circuitry and extend laterally and outwardly from an outer perimeter of the frame. The gel in the cavity covers the electronic circuitry.

A die stack structure is provided. The die stack structure includes a non-extended semiconductor die, an extended semiconductor die, and an extended top semiconductor die are stacked vertically over a base semiconductor die. The extended semiconductor die and the extended top semiconductor die each have an extension portion extending horizontally outward from one side thereof as compared to the non-extended semiconductor die. An encapsulant layer is formed over the base semiconductor die and encapsulates the sidewalls of the non-extended semiconductor die, the extended semiconductor die, and the extended top semiconductor die. Thermally conductive features are formed in the extension portion of the extended semiconductor die and in the extension portion of extended top semiconductor die. A thermally conductive structure is embedded in the encapsulant layer, extending vertically between the extended semiconductor die and the extended top semiconductor die, and contacting the thermally conductive features.

The present disclosure relates to a ceramic substrate unit and a manufacturing method therefor, in which the volume of an upper electrode bonded to an upper metal layer of a ceramic substrate is calculated, and multiple separated heat sinks are formed so as to have a predetermined volume corresponding to the volume of the upper electrode, and thus warpage occurring at a high temperature may be suppressed.

Disclosed techniques enable provide techniques for improved power delivery for wafer-scale integration. A wafer-scale integration interposer (WSII) is accessed. A front side of the WSII is bonded to a plurality of chiplets. The WSII includes through-silicon vias (TSVs).

Modular power substrates (MPSs) are inserted into an isometric grid array (IGA). A back side of the IGA includes a plurality of external compression pins. The MPSs are coupled to the chiplets. The coupling includes compressing, by one or more compression plates, one or more elastomer sheets between the MPSs and the TSVs. The compressing is based on the external compression pins. The MPSs are coupled to DC-to-DC power converters. The coupling is based on sockets. DC power is sent by the DC-to-DC power converters to the chiplets. The sending is based on the MPSs, the one or more elastomer sheets, and the TSVs.

A method includes attaching a permeable plate to a metal lid, with the permeable plate including a metallic material, and dispensing a liquid-metal-comprising media to a first package component. The first package component is over and bonded to a second package component. The liquid-metal-comprising media includes a liquid metal therein. The method further includes attaching the metal lid to the second package component. During the attaching, the liquid-metal-comprising media migrates into the permeable plate to form a composite thermal interface material.

Encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture different from the first texture.