A composition for semiconductor processing includes abrasive particles, and a dishing control additive, comprising a first dishing control additive and a second dishing control additive. The first dishing control additive includes a compound having a betaine group and a salicylic group or a derivative thereof, and the second dishing control additive includes an azole-based compound. The first dishing control additive includes 0.07 parts by weight or more based on 100 parts by weight of the abrasive particles, and the second dishing control additive includes 0.13 parts by weight or less based on 100 parts by weight of the abrasive particles.

A slurry composition for polishing metal and a method of manufacturing an integrated circuit device, the slurry composition includes a first organic polishing booster including a cationic polymer salt that includes a quaternary ammonium cation; a second organic polishing booster including an organic acid; an oxidizer; a pH adjuster; 0 wt % to about 0.1 wt % of an inorganic abrasive; and water.

A film thickness measuring apparatus and an end point detector monitor a film thickness of a conductive film based on an output of an eddy current sensor disposed in a polishing table. The output of the eddy current sensor includes an impedance component, and when a resistance component and a reactance component of the impedance component are associated with the respective axes of a coordinate system having two orthogonal coordinate axes, at least some points on the coordinate system corresponding to the impedance component form at least a part of a circle. The film thickness measuring apparatus determines a distance between a point on the coordinate system and the center of the circle, determines the film thickness from the impedance component and corrects the determined film thickness using the determined distance.

An apparatus includes a through-silicon via (TSV) including a conductive material; a first contact plug having an upper surface and a bottom surface directly connected to an upper surface of the TSV; a first wiring directly connected to the upper surface of the first contact plug; a second wiring having an upper surface; a second contact plug having an upper surface and a bottom surface directly connected to the upper surface of the second wiring; and a third wiring directly connected to the upper surface of the second contact plug; wherein the first wiring and the third wiring are in a substantially same level.

A semiconductor device structure includes a gate structure formed over a substrate. The semiconductor device structure also includes a source/drain structure formed beside the gate structure. The semiconductor device structure further includes a contact structure formed over the source/drain structure. The semiconductor device structure also includes a first cap layer formed over the contact structure. The semiconductor device structure further includes a dielectric structure extending from a top surface of the first cap layer into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.

Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

A method of forming a semiconductor structure includes forming a conductive feature in a first dielectric layer, depositing a second dielectric layer over the conductive feature, forming a first opening in the second dielectric layer to expose a top surface of the conductive feature, selectively depositing an inhibitor film on the top surface of the conductive feature, depositing a dielectric barrier layer on sidewalls of the first opening, removing the inhibitor film to expose the top surface of the conductive feature, depositing a conductive material over the dielectric barrier layer and filling the first opening, and performing a planarization process to expose the dielectric barrier layer.

A semiconductor device, including: a semiconductor substrate having a main surface; an interlayer insulating film provided on the main surface of the semiconductor substrate; a contact hole penetrating through the interlayer insulating film to reach the semiconductor substrate; a plug electrode embedded in the contact hole; a first barrier metal provided on the interlayer insulating film, the first barrier metal being apart from the plug electrode; and a front electrode provided on the first barrier metal and the plug electrode.

A method for fabricating an integrated circuit (IC) includes forming a silicon substrate and doping the silicon substrate with impurities. The method includes sequentially depositing and patterning multiple layers over the silicon substrate, wherein the layers comprise at least a dielectric layer, a metallization layer, an organic polarized layer (OPL), and a photoresist layer. The method includes etching one or more of the layers to create features including vias or trenches. The method includes cooling the IC to a temperature of around 20 C. or lower. The method includes stripping at least the organic planarization layer (OPL) and photoresist residue using ammonia (NH3) plasma to expose the metallization layer and depositing a metal in the vias or trenches.