A method of manufacturing a semiconductor device includes providing a structure including a first insulating pattern and a metal pattern disposed on a substrate, performing a cleaning process on the structure, exposing the structure to a reducing agent, forming, selectively, a passivation layer on the metal pattern, forming, selectively, a second insulating pattern on the first insulating pattern, and performing thermal processing on the structure.

The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

Provided are conductive structures located within dielectric material, and methods for fabricating such structures and devices. An exemplary method includes providing a substrate having a conductive feature in a first dielectric layer; depositing a second dielectric layer over the conductive feature and the first dielectric layer; etching the second dielectric layer to form a cavity through the second dielectric layer, wherein the cavity has a bottom with a convex profile; depositing a barrier layer along the bottom of the cavity; and depositing a conductive material in the cavity to form a structure electrically connected to the conductive feature.

The present disclosure provides a manufacturing method of a semiconductor structure including the following steps. A trench is formed between bit lines. A seed layer is deposited in the trench, and a first contact layer is deposited on the seed layer in the trench. A second contact layer is deposited on the first contact layer to fill the trench, in which a second doping concentration of the second contact layer is lower than a first doping concentration of the first contact layer. An annealing process is performed on the first contact layer and the second contact layer, such that dopants in the first contact layer diffuse into the second contact layer to form a contact plug including the first contact layer and the second contact layer.

A semiconductor structure includes a first dielectric layer, a first via and a second via disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the first via, and the second via, a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer, a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer, a first barrier layer extending along sidewalls and a top surface of the first conductive line, and a second barrier layer extending along sidewalls and a top surface of the second conductive line. The bottom portion of the second dielectric layer includes an air gap between the first conductive line and the second conductive line.

A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

Some embodiments relate to an integrated chip having a memory cell over a substrate. The memory cell includes a first electrode. An electrode contact is on an upper surface of the first electrode. A width of an upper surface of the electrode contact is greater than a width of the upper surface of the first electrode and a thickness of the electrode contact. A first conductive interconnect structure contacts the upper surface of the electrode contact. A width of the first conductive interconnect structure is greater than the width of the upper surface of the electrode contact. A second conductive interconnect structure overlies the first conductive interconnect structure. Thicknesses of the first and second conductive interconnect structures are greater than the thickness of the electrode contact.

A substrate cleaning apparatus may include a first roll member and a second roll member including a copolymer of a first water-soluble polymer and a second water-soluble polymer. The first roll member may include a first roll body extending in a first direction and first protrusions on a surface of the first roll body. The second roll member may include a second roll body extending in the first direction and second protrusions on a surface of the second roll body.