Semiconductor structures and methods of fabrication are provided. A semiconductor structure includes an interconnect structure lying over a semiconductor substrate and having a top metal feature; a pad lying over the interconnect structure; and an extended conductive line having a proximal end electrically connected to the pad and extending to a distal end, wherein the extended conductive line include a proximal portion extending in a first direction and a non-proximal portion extending in second direction transverse to the first direction, and wherein the extended conductive line is electrically connected to the top metal feature.

Provided is a bonding structure including a first dielectric layer, a first non-twinned metal layer, a first twinned metal layer, and a first transition layer. The first dielectric layer has a first inner sidewall defining a first via hole and a first trench on the first via hole. The first non-twinned metal layer is filled in the first via hole. The first twinned metal layer is disposed over the first non-twinned metal layer and within the first trench. The first transition layer is sandwiched between the first non-twinned metal layer and the first twinned metal layer.

The present disclosure provides a method for forming a semiconductor device. A first wafer including a first substrate and a first interconnection layer formed on the first substrate is provided. A second wafer including a second substrate and a second interconnection layer formed on the second substrate is provided. The second wafer is stacked on the first wafer. A thinning process is performed on the second substrate of the second wafer. An edge trimming process is performed to remove portions of the second interconnection layer and the second substrate along a perimeter of the second wafer, wherein the edge trimming process results in the first wafer having a recessed surface. A protective layer, surrounding a sidewall of the thinned and edge-trimmed second wafer, is formed on the recessed surface to form a wafer stack structure.

A semiconductor device and method of fabrication are described. The device includes a semiconductor RFID IC base layer; a passivation layer located over the base layer and including a metal insert within the passivation layer; a repassivation layer located over the passivation layer and the metal insert; an assembly pad layer located over the repassivation layer. The device includes a first region R1 of the device, where a height of the repassivation layer is given by d.sub.1, and a region R1 is provided with an assembly pad in the assembly pad layer over the repassivation layer that has an area A.sub.1. The device includes an nth region RN of the device, where the height of the repassivation layer is given by d.sub.n, where d.sub.1>d.sub.n, and the region RN is provided with an assembly pad in the bump layer over the repassivation layer, which has an area A.sub.n, where A.sub.n>A.sub.1.

Embodiments disclosed herein include electronic devices and methods of forming electronic devices. In an embodiment, an electronic device comprises a die. In an embodiment, the die comprises a semiconductor substrate, a bump field over the semiconductor substrate, and a V-groove into the semiconductor substrate, wherein the V-groove extends to an edge of the semiconductor substrate. In an embodiment, the V-groove is free from conductive material. In an embodiment, the electronic device further comprises an optical fiber inserted into the V-groove.

A first integrated circuit (IC) die and a second IC die are bonded together in a stacked arrangement in a device package. The second IC die includes at least one bonding structure that is bonded to the first IC die. A barrier layer on sidewalls of a top portion of the bonding structure is removed and replaced with a dielectric liner that is formed on the sidewalls after the bonding structure is formed. The dielectric liner has a material removal rate (e.g., for processes such as CMP, grinding, and/or chemical-based surface cleaning) that is closer to the material removal rate of the bonding structure than the material removal rate of the barrier liner. This reduces the likelihood of the formation of voids in the bond between the first IC die and the second IC die that might otherwise occur due to excessive material removal from the bonding structure.

A chip package with electromagnetic interference (EMI) shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. A peripheral wall is formed around at least one first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The flat portion of the insulating layer is covered with the EMI shielding layer which is isolated and electrically insulated from a pad in the first opening by the peripheral wall of the insulating layer. Thereby problems of the chip including fast increase in temperature and electromagnetic interference can be solved effectively.

A semiconductor device includes a first semiconductor component including a first semiconductor substrate and a first wiring structure, and a second semiconductor component including a second semiconductor substrate and a second wiring structure. A first surface of the first semiconductor component and a second surface of the second semiconductor component are bonded together. Assuming that regions having circumferences respectively corresponding to shapes obtained by vertically projecting the first surface, the second surface, the first wiring structure, and the second wiring structure on a virtual plane are first to fourth regions, respectively, an area of the first region is smaller than an area of the second region, the entire circumference of the first region is included in the second region, an area of the fourth region is smaller than an area of the third region, and the entire circumference of the fourth region is included in the third region.

Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

A method includes forming a passivation structure over a first conductive feature; forming an opening in the passivation structure to expose the first conductive feature; forming a protection layer over the passivation structure and within the opening, wherein the protection layer over the passivation structure has a first thickness; recessing a portion of the protection layer to form a recess, wherein the recess exposes the first conductive feature, wherein a second thickness of the protection layer at a sidewall of the recess is smaller than the first thickness; and forming a second conductive feature over the protection layer and within the recess.