In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

A semiconductor device includes a lower structure including a substrate and a cell structure on the substrate and a plurality of interconnection layers, which are stacked on the lower structure in a first direction extending perpendicular to a top surface of the substrate. An uppermost interconnection layer of the plurality of interconnection layers includes uppermost conductive lines. Each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern, an upper metal compound pattern, and a capping pattern, which are sequentially stacked in the first direction. The lower metal compound pattern, the metal pattern, and the upper metal compound pattern include a same metallic element.

The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first dielectric material; a second dielectric material separated from the first dielectric material; a memory cell string including a pillar extending through the first and second dielectric materials, the pillar including a portion between the first and second dielectric materials; an additional dielectric material contacting the portion of the pillar; a conductive material contacting the additional dielectric material; and a tungsten structure including a portion of tungsten contacting the conductive material, wherein a majority of the portion of tungsten is beta-phase tungsten.

In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

A semiconductor device includes a substrate, a first wiring pattern on an upper surface of the substrate, and a second wiring pattern on the upper surface of the substrate. The first wiring pattern includes a first crystal and a second crystal adjacent to the first crystal in a horizontal direction. A crystal orientation of each of the first crystal and the second crystal is in a vertical direction perpendicular to the upper surface of the substrate. An interface between the first crystal and the second crystal extends in the vertical direction. The second wiring pattern is spaced apart from the first wiring pattern in the horizontal direction.

A semiconductor device including an insulating structure, and a conductive structure in the insulating structure may be provided. The conductive structure includes a barrier layer, an anti-migration layer on the barrier layer, a liner on the anti-migration layer, a conductive layer on the liner, and a capping layer covering a top surface of the barrier layer and a top surface of the anti-migration layer. The capping layer and the liner include Co. The anti-migration layer includes Mn.

A semiconductor device including an insulating structure, and a conductive structure in the insulating structure may be provided. The conductive structure includes a barrier layer, an anti-migration layer on the barrier layer, a liner on the anti-migration layer, a conductive layer on the liner, and a capping layer covering a top surface of the barrier layer and a top surface of the anti-migration layer. The capping layer and the liner include Co. The anti-migration layer includes Mn.

The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via. The method further includes providing a planar dielectric material in contact with the first electrically conductive line, forming an opening in the planar dielectric material, filling the opening with a planar electrically conductive material, forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material, providing a hard mask comprising a set of parallel lines, and etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.

A semiconductor structure includes a base provided with a conductive contact hole, a metal sulfide layer formed in the conductive contact hole and covering a bottom wall of the conductive contact hole, a semi-metal layer formed on a surface of the metal sulfide layer, a barrier layer covering a surface of the semi-metal layer and a sidewall of the conductive contact hole and a conductive contact structure disposed in an accommodation hole delimited by the barrier layer.