An electronic package is provided which includes a continuous stiffener element (i.e., frame) located around a semiconductor die. The continuous stiffener element has a coefficient of thermal expansion (CTE) that closely matches the CTE of a carrier substrate that is located beneath the semiconductor die. The closely matched CTA between the continuous stiffener element and the carrier substrate reduced warpage in an electronic package containing the same. A molding component can be disposed between the continuous stiffener element and the semiconductor die. The electronic package having the reduced warpage can be used as a component of an electronic packaging structure.

Provided is a semiconductor package including a package substrate, a stacked structure mounted on the package substrate, and a heat dissipation structure mounted on the stacked structure, wherein the stacked structure includes a lower die, a passive device chip, a second upper die arranged apart from the passive device chip on the lower die, and a first upper die mounted on the passive device chip, and wherein the lower die includes a voltage control chip, the passive device chip includes a capacitor, and the package substrate includes an inductor.