Disclosed is a method for preparing a display substrate, including: providing a driving substrate; wherein the driving substrate includes: a base substrate; a pixel driving circuit layer; a first pad and a second pad, spaced from each other, and connected to the pixel driving circuit layer; and an electrostatic protection alignment, spaced from the first pad; and transferring a light-emitting element to the driving substrate, such that an anode of the light-emitting element is connected in alignment with the first pad and a cathode of the light emitting-element is connected in alignment with the second pad. The first pad includes a first toothed tip arranged on a side of the first pad facing the electrostatic protection alignment, and the electrostatic protection alignment includes a second toothed tip arranged on a side of the electrostatic protection alignment facing the first pad.

One exemplary method of forming a semiconductor structure having a platinum-based solder body contact includes providing a semiconductor structure having a passivation layer over a surface thereof, the passivation layer having a window exposing a portion of a top metal pad, and forming a barrier metal stack over the passivation layer and the portion of the top metal pad, the barrier metal stack including a tantalum nitride (TaN) layer and a tantalum (Ta) layer. The method further includes forming a solder body contact layer comprising platinum (Pt) over the barrier metal stack, and patterning the solder body contact layer and the barrier metal stack to form the platinum-based solder body contact over the portion of the top metal pad.

An example semiconductor device includes a first semiconductor structure including a first semiconductor substrate and a first interconnection layer disposed on the first semiconductor substrate and including first interconnection structures and first bonding pads connected to the first interconnection structures and exposed on an upper surface; a second semiconductor structure including a second semiconductor substrate disposed on the first semiconductor structure, and a second interconnection layer disposed on the second semiconductor substrate, and including second interconnection structures, and second bonding pads connected to the second interconnection structures and exposed on a lower surface; and a buffer structure extending from at least one of side surfaces of the first semiconductor structure and the second semiconductor structure to a bonding surface between the first interconnection layer and the second interconnection layer.

Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.

A semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is disposed on and electrically connected to the semiconductor substrate. The interconnect structure includes stacked interconnect layers. Each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. The interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. The first via electrically connected to the interconnect wiring. The second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. The conductive bump is disposed on the interconnect structure. The conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.

The present disclosure provides an electronic device including an electronic unit including a first conductive pad, a protective layer disposed on the electronic unit, a packaging layer surrounding the electronic unit and the protective layer, a conductive component disposed in the protective layer and overlapped with the first conductive pad, a bonding component disposed on the conductive component and overlapped with the first conductive pad, and an external component disposed on the bonding component and including a second conductive pad overlapped with the first conductive pad. The external component is electrically connected to the first conductive pad through the bonding component.